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Original question:

TDA4VH-Q1: startup issue for TDA4VH

TDA4VH-Q1: TDA4VH BRING UP ISSUE

wang kun
Prodigy 140 points
Part Number: TDA4VH-Q1
Other Parts Discussed in Thread: TDA4VH, DRA821, TDA4VM

Tool/software:

Hello TI experts, I've encountered some issues while debugging the TDA4VH and need your support. Here's the background:
  1. The schematic was designed by us；
  2. All power rails have the correct voltage；
  3. MCU_PORZ and MCU_RESETSTATZ have been pulled up to 1.8V；
  4. PORZ is pulled up to 1.8V, but RESETSTATZ remains low, and SOC_SAFETY_ERRORN is also continuously low；
  5. For boot: the clock configuration is 25M, and I've also checked the voltage levels of BOOTMODE, which are configured as follows；
  6. We want to debug through the UART, but the voltage levels of the UART (K34, K35, AK35, AK38) are all 0；
Where might the problem lie? Thank you for your answer.
  • 0
    TI__Expert 6995 points

    Please confirm you have reviewed your SCH using the recommended Jacinto7 SCH Checklist applications note available on TI website (https://www.ti.com/lit/pdf/sprad91).  Together with the applications note, the SCH checklist xls file has embedded instructions on how to use it & macros must be enabled to enable Excel checklist to select specific J7 SoC targeted PN (TDA4VM, DRA821, TDA4AL, TDA4AH, etc) which then populates the correct SoC SCH checklist.

    Here's an overview of the TI's SCH Review Process:

    Step 1: Customers complete checklist review on their finished SCH.  The checklist provides the ability for customers to review their design and ask specific questions for areas where they have questions or concerns. Jacinto7 EVM SCHs for specific SoC PNs are available on the TI website, They should be downloaded and used as a reference during customer SCH design and checklist review for comparison.

    Step 2: TI then reviews the specific design questions/areas of concern and provide feedback & guidance as needed.

    In addition, please find the PMIC SCH Checklist (https://www.ti.com/lit/zip/slvc804) in Excel format as well if you have used one of the TI recommended power solutions.

  • 0 in reply to Bill McCracken
    Prodigy 140 points
    Hello Bill,
    I double - checked the schematic checklist at the end of the design, and the TI expert also replied to the design issues.
    The problem I'm now encountering is that RESETSTATZ remains low. What could cause RESETSTATZ to not release?
    The checklist, power sequencing, ripple voltage, and other parameters have been verified. However, the voltage rise slope of MCU_BOOTMODE0 is relatively slow. Could this affect the boot signal sampling?"As shown in the schematic, the actual PCB uses a 10K pull-up resistor (no pull-down). The signal is directly connected to the TDA4 with no other connections.Configure 25M clock.

  • 0 in reply to wang kun
    TI__Expert 6995 points

    Releasing the RESETSTATz & MCU_RESETSTATz signals are dependent on the SoC boot process as described in the TRM, snap-shots below.

    Do you have a scope-shots captured showing PORz rising edge (at the end of the power up seq) vs each MCU_BOOTMODE input? 

  • 0 in reply to Bill McCracken
    TI__Expert 6995 points

    If RESETSTATz is not releasing, then the SoC is NOT exiting the reset sequence.  Latched boot values do not matter at this point as ROM code has not started executing yet.  For RESETSTATz to release (go high), the SoC needs correct input supply voltages, proper input clock on WKUP_OSC0 (pins T38 & U37 for a crystal), and proper MCU_PORz & PORz input reset signal operation per power up sequence timing.

    DM text: