Other Parts Discussed in Thread: TWL6041, TWL6040
Hi,
In OMAP4430 TRM (SWPU231W) section 23.9.5.1.7 specifically states that the IRQ status bit should be cleared before servicing the relevant information register.
However, experimentation has show that when handling the UNDERFLOW event (bit 1) if the IRQ status bit is cleared before clearing this the INFO event bit, the interrupt is re-triggered.
Does this represent an exception to algorithm in section 23.9.5.1.7?
Thanks, Marc