DMA in omap 3530 's mcbsp

	hello ,I have a questions in the omap3530 , when I used DMA in mcbsp ,I found my send date in DX is wrong,
 but I can see the CLKX and FSX signals on scope,I used MCBSP1, CLKX and FSX come from internal generation,when I 
send date which is 0x1,I found is 0x48474008 on scope.I only found register the DMA4_CSACi which  means Current source 

address counter value is 0xffdff000; and DMA4_CDACi which means Current destination address counter value is 0x48474008, 

but I send date is 0x1,why date is wrong ,and I send a date to DX is right, but used DMA is wrong,s, it is my code ,could 

you find the mistake if is as my thought, thanks.     


#include "McBSP.h"
#include "PRCM.h"
#include "CONTROL.h"
#include "operations.h"
#include "mcbsp_lib.h"
#include "DMA.h"
#include "dma_lib.h"

#define MY_MCBSP  MCBSP1

int main (void)
{
int i;
static char *mcbsp_buff=NULL;
dma_addr_t tx=0;

mcbsp_buff=dma_alloc_coherent(NULL,1024,&tx,0);
for(i=0;i<1024,i++)
*mcbsp_buff=0x1;

 // Setup the DMA 
  dmaSetCsdp(CHAN14, SRC_LITTLE_ENDIAN, SRC_ENDIAN_ADAPT, DST_LITTLE_ENDIAN, DST_ENDIAN_ADAPT, 
             WRITE_POSTED, DST_NO_BURST, DST_UNPACKED, SRC_NO_BURST, SRC_UNPACKED, SCALAR_32BITS);
 dmaSetCcr(CHAN14, LOW_WR_PRIORITY, EN_BUFF, TRG_SRC, NO_PREFETCH, DIS_SUPER, DIS_TRANS_COPY, DIS_CONST_FILL, 
            DST_AMODE_POST_INC, SRC_AMODE_CONST, DIS_SUSPEND, DIS_CHANNEL, LOW_RD_PRIORITY, TRANS_FRAME,          

DMA_MCBSP1_DMA_TX);
dmaConfigTransfer(CHAN14, 16, 1, (MY_MCBSP+MCBSPLP_DRR_REG), mcbsp_buff, 1, 0, 1, 0);
 dmaEnableChannel(CHAN14);	
  /////////////////////////////////////////////////////////////
  // Select clock sources and switch on Switch on the clocks
  cmEnableClock96M(); 
  mcbspEnableIclk(MY_MCBSP);
  mcbspSelectClksSource(MY_MCBSP, INTERNAL_FCLK);
  mcbspEnableFclk(MY_MCBSP);
  
  mcbspSet4Pin(MY_MCBSP);  // Sets McBSP1 to 4 pin mode. 
  
  /////////////////////////////////////////////////////////////
  // reset module
  mcbspReset(MY_MCBSP, 1);  
/////////////////////////////////////////////////////////////
  // Configure  receiver
  mcbspSetTxMode(MY_MCBSP, CLK_INTERNAL, CLKX_DRIVE_FALL,  SYNC_INTERNAL, SYNC_ACTIVE_LOW, HALF_CYCLE, DXENA_OFF, 

XCLK_FREE, FSX_GATED);  

  /////////////////////////////////////////////////////////////
  // Set up frames
  mcbspTxFrameSetup(MY_MCBSP, SINGLE_PHASE, MSB_FIRST, DELAY_0BIT, 4, 1,WORD_8BITS); 
  /////////////////////////////////////////////////////////////
  // Program the Sample Rate generator  
  mcbspSetupSrg(MY_MCBSP, CLKS, CLKS_RISE, SRG_FREE, 32, 8, 255);      

  mcbspSetTxThresh(MY_MCBSP, 127);

 OUT_REGL(CONTROL_PADCONF_MCBSP1_CLKR, 0x01000100);                       // 31:16 = mcbsp1_fsr         15:0 = mcbsp1_clkr
  OUT_REGL(CONTROL_PADCONF_MCBSP1_DX, 0x01000100);	                       // 31:16 = mcbsp1_dr          15:0 mcbsp1_dx 

                   
  CLRBIT_REGL(CONTROL_PADCONF_MCBSP1_CLKX, 0xFFFF);                        // 31:16 = uart3_cts_rctx     15:0 = mcbsp1_clkx
  SETBIT_REGL(CONTROL_PADCONF_MCBSP1_CLKX, 0x0100);                        // 31:16 = uart3_cts_rctx     15:0 = mcbsp1_clkx

 mcbspRemoveResetTx(MY_MCBSP);
return 0;
}

0 PaulM over 13 years ago

TI__Mastermind 27945 points

Tao

I see a few issues in the CCR setup:

Your current command:

dmaSetCcr(CHAN14, LOW_WR_PRIORITY, EN_BUFF, TRG_SRC, NO_PREFETCH, DIS_SUPER, DIS_TRANS_COPY, DIS_CONST_FILL,
DST_AMODE_POST_INC, SRC_AMODE_CONST, DIS_SUSPEND, DIS_CHANNEL, LOW_RD_PRIORITY, TRANS_FRAME, DMA_MCBSP1_DMA_TX);

Should be:

dmaSetCcr(CHAN14, LOW_WR_PRIORITY, EN_BUFF, TRG_DEST, NO_PREFETCH, DIS_SUPER, DIS_TRANS_COPY, DIS_CONST_FILL,
DST_AMODE_CONST, SRC_AMODE_POST_INC, DIS_SUSPEND, DIS_CHANNEL, LOW_RD_PRIORITY, TRANS_FRAME, DMA_MCBSP1_DMA_TX );

1. The DMA needs to be triggered by the McBSP fifo - TRG_SRC
2. The destination is a FIFO so the addressing mode needs to be constant - DST_AMODE_CONST
3. The source is DDR which is typically sequential so the the addressing mode needs to be incrementing - SRC_AMODE_POST_INC

Also, your McBSP TX DMA Threshold needs to match the number of frame elements. Your DMA is setup for 16 elements therefore the the McBSP should be configured using the following commend:

mcbspSetTxThresh(MY_MCBSP, 16);

I've attached an example I created for the McBSP which demonstrates TX & RX with DMA.

Paul

MCBSP_TXRX_DMA_1.zip

0 tao wu over 13 years ago in reply to PaulM

Prodigy 100 points

paul

thank you answer,I used you method,but the DMA also can not send date,when I send a series date ,I only found register the DMA4_CCRi which WR_ACTIVE via value is 0; it means Channel is not active on the write port,I can active on the read port,but why the the write port is not active,thanks

tao wu

0 PaulM over 13 years ago in reply to tao wu

TI__Mastermind 27945 points

Tao

The WR_ACTIVE is a status bit that you can use to to check if the DMA channel is actively writing data. This needs to be '0' before re-enabling the DMA channel.

Paul

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DMA in omap 3530 's mcbsp