Tool/software:
Dear TI Support Team,
I am currently working on a project involving a custom AM3359-based EVM board. We are aiming to achieve Ethernet latency below 1ms for 100Mbps communication using the DP83867ERGZ Ethernet PHY.
To meet this performance target, we would like to explore PHY configuration optimization techniques, particularly tuning the configuration registers of the DP83867ERGZ for low-latency operation.
We kindly request your support and guidance on the following:
PHY Register Settings:
What specific register configurations or optimizations are recommended to reduce latency for the DP83867ERGZ at 100Mbps?
Are there any settings that can bypass or minimize internal delays (e.g., FIFO thresholds, interrupt configurations, delay lines)?
MAC-PHY Interface Tuning:
Are there any recommendations for optimizing the RGMII interface between the AM3359 MAC and the DP83867ERGZ for minimal latency?
Linux Driver Modifications:
Are there any driver-level optimizations or patches (e.g., in CPSW or PHY drivers) that TI recommends to reduce latency in the Linux SDK for the AM335x platform?
Testing and Measurement Procedure:
Could you please share the best practices or tools recommended by TI to measure Ethernet latency accurately?
Is there a test suite or benchmark methodology (e.g., using netperf, iperf, or hardware timestamping) that TI uses internally?
We are currently using the TI Processor SDK Linux for AM335x (Version 05.00.00.15) and the Linux kernel 4.14.40. We are prepared to apply any relevant software or hardware recommendations to achieve this optimization goal.
Your support in this matter would be highly valuable for our development timeline. Please let us know if any additional information about our board design or software environment is required.
Thank you for your time and assistance.
Best regards,
Raj
