• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 99 subscribers
  • Views 464 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

McASP on OMAP-L138

Boris Ruvinsky
Expert 1410 points
Other Parts Discussed in Thread: OMAP-L138

Dear E2E:

Thank you for your help.

OMAP-L138 data sheet (SLVSQ9), page154 has "McASP Timing reguirements".

The timing parameters 5 and 6 and 7 in Table 5-65 are different depending of AHCLKR/X internal  or AHCLKR/X external output.

Is Data sheet correct?

As I understood - if AHCLKR/X is external output - that means it was generated internally. Is this correct?

Can you please explain in more details - what "AHCLKR/X ext output" means? What is the source for AHCLKR/X in this case?

Thank you ,

Boris Ruvinsky

  • 0
    TI__Guru* 83965 points

    Boris

    Sorry for the delay in response. The McASP expert will respond back to this in a day or two.

    A few things to note

    1) Looks like it should have been ACLKR/X not AHCLKR/X , and "H" is a typo (but will need for the McASP expert to confirm).

    2) The external output mode is a unique mode that is never really used by any customer, and has to do with pad loopback mode that is typically used for internal timing analysis etc. So I think you can ignore that mode.

    Regards

    Mukul

  • 0 in reply to Mukul Bhatnagar
    TI__Intellectual 2350 points

    Hi, Mukul is right.

    #1. It's a typo.

    #2.External output basically means that you internally generate the clock, but set the pin up as an input.  So you drive the clock out of the output buffer (output), but take it back into the input buffer as if it were an external source (external).  FYI, here's the relevant info from the McASP user guide.  As Mukul said, nobody really uses it.

    Finally, there is an important advantage to having separate control of pin direction (by PDIR), and the
    choice of internal versus external clocking (by CLKRM/CLKXM). Depending on the specific device and
    usage, you might select an external clock (CLKRM = 0), while enabling the internal clock divider, and the
    clock pin as an output in the PDIR register (PDIR[ACLKR] = 1). In this case, the bit clock is an output
    (PDIR[ACLKR] = 1) and, therefore, routed to the ACLKR pin. However, because CLKRM = 0, the bit clock
    is then routed back to the McASP module as an "external" clock source. This may result in less skew
    between the clock inside the McASP and the clock in the external device, thus producing more balanced
    setup and hold times for a particular system. As a result, this may allow a higher serial clock rate interface.


    Bobby T.

  • 0 in reply to Tufino
    Expert 1410 points

    Hi Bobby.

    Thank you very much for your respond and help.

    I was always thinking that #1 was a typo, thank you for clarifying that.

    Is there any timing available for AHCLKX/R to ACLKX/R when AHCLKX/R (external) are used to generate ACLKX/R?

    There should be some timing for that but I can't find any in DS.

    Thank you for your help,

    Boris