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J721S2XSOMXEVM: J721S2 / J721E USB 3.1 ports only operate at USB 2.0 speed (SDK 10.01.00.04)

zemiao liu
Prodigy 40 points
Part Number: J721S2XSOMXEVM

Tool/software:

Dear TI Support Team,

I'm working with both the J721S2 and J721E EVM boards, and I'm experiencing issues with USB 3.x connectivity:

Boards and SDK Versions:

  • J721S2 using rtos-j721s2-evm-10_01_00_04

  • J721E using rtos-j721e-evm-10_01_00_04

Issues observed:

J721S2:

  • The USB Type-A port is not detected at all.

  • The USB Type-C port works, but it only connects USB devices at High-Speed (USB 2.0 / 480 Mbps).

  • I have tested multiple verified USB 3.0/3.1 flash drives and cables, all of which work correctly at 5 Gbps on a PC.

J721E:

  • Both the Type-A and Type-C ports are functional, but all USB 3.x devices are still limited to USB 2.0 speed (480 Mbps).

Other Checks:

  • The ports are labeled as USB 3.1 capable.

  • The flash drives and cables are confirmed to support USB 3.0/3.1.

  • lsusb -t always shows 480M speed regardless of port or board.

  • dmesg confirms that the host controllers support USB 3.0 (xhci-hcd, SuperSpeed capable).

  • Still, devices are always negotiated as USB 2.0 (High-Speed).

Questions:

  • Is there any known limitation with RTOS SDK 10.01.00.04 that affects USB 3.x negotiation?

  • Any debugging tips or recommended device connection paths to verify USB 3.x functionality?

Best regards,

Liu

  • 0
    TI__Genius 11280 points

    HI Liu,

    We do not provide support for USB drivers in RTOS. We can help you with any issues faced in USB in linux as we provide support for that.

    Please do let us know if you are facing issues in USB linux in the future.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 40 points

    Hi Gokul,

    Thank you for the clarification.

    Yes, the issue I’m facing is on Linux. When I connect a USB 3.0 flash drive to the USB Type-C port (which is supposed to support USB 3.1), it only gets recognized as a USB 2.0 device both on J721E and J721S2.

    Fullscreen 0878.USB.log Download 
    [   43.500749] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   43.506356] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 1
[   43.514235] xhci-hcd xhci-hcd.21.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   43.523747] xhci-hcd xhci-hcd.21.auto: irq 784, io mem 0x06010000
[   43.529985] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   43.535557] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 2
[   43.543294] xhci-hcd xhci-hcd.21.auto: Host supports USB 3.0 SuperSpeed
[   43.550385] hub 1-0:1.0: USB hub found
[   43.554159] hub 1-0:1.0: 1 port detected
[   43.558327] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   43.567246] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   43.575043] hub 2-0:1.0: USB hub found
[   43.578889] hub 2-0:1.0: 1 port detected
[   43.583301] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   43.592082] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   43.600233] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   43.610168] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   43.617778] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   43.627856] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   43.636473] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   43.669371] xhci-hcd xhci-hcd.21.auto: remove, state 1
[   43.674534] usb usb2: USB disconnect, device number 1
[   43.680197] xhci-hcd xhci-hcd.21.auto: USB bus 2 deregistered
[   43.686025] xhci-hcd xhci-hcd.21.auto: remove, state 84
[   43.691279] usb usb1: USB disconnect, device number 1
[   43.700448] xhci-hcd xhci-hcd.21.auto: USB bus 1 deregistered
[   43.852694] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   43.858310] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 1
[   43.866189] xhci-hcd xhci-hcd.21.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   43.875687] xhci-hcd xhci-hcd.21.auto: irq 784, io mem 0x06010000
[   43.881897] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   43.887467] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 2
[   43.895201] xhci-hcd xhci-hcd.21.auto: Host supports USB 3.0 SuperSpeed
[   43.902278] hub 1-0:1.0: USB hub found
[   43.906101] hub 1-0:1.0: 1 port detected
[   43.911046] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   43.919838] hub 2-0:1.0: USB hub found
[   43.923635] hub 2-0:1.0: 1 port detected
[   43.928030] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   43.935715] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   43.944006] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   43.952185] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   43.966365] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   43.974060] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   43.982238] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   43.990418] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   44.021451] xhci-hcd xhci-hcd.21.auto: remove, state 1
[   44.026605] usb usb2: USB disconnect, device number 1
[   44.032814] xhci-hcd xhci-hcd.21.auto: USB bus 2 deregistered
[   44.038629] xhci-hcd xhci-hcd.21.auto: remove, state 84
[   44.043901] usb usb1: USB disconnect, device number 1
[   44.049619] xhci-hcd xhci-hcd.21.auto: USB bus 1 deregistered
[   44.204776] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   44.210416] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 1
[   44.218297] xhci-hcd xhci-hcd.21.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   44.227799] xhci-hcd xhci-hcd.21.auto: irq 784, io mem 0x06010000
[   44.234010] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   44.239579] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 2
[   44.247312] xhci-hcd xhci-hcd.21.auto: Host supports USB 3.0 SuperSpeed
[   44.254411] hub 1-0:1.0: USB hub found
[   44.258242] hub 1-0:1.0: 1 port detected
[   44.262627] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   44.270850] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   44.271309] hub 2-0:1.0: USB hub found
[   44.282177] hub 2-0:1.0: 1 port detected
[   44.286188] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   44.296631] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   44.312178] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   44.323645] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   44.331722] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   44.339893] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   44.348077] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   44.373491] xhci-hcd xhci-hcd.21.auto: remove, state 1
[   44.378661] usb usb2: USB disconnect, device number 1
[   44.384821] xhci-hcd xhci-hcd.21.auto: USB bus 2 deregistered
[   44.390647] xhci-hcd xhci-hcd.21.auto: remove, state 84
[   44.395896] usb usb1: USB disconnect, device number 1
[   44.401602] xhci-hcd xhci-hcd.21.auto: USB bus 1 deregistered
[   44.556834] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   44.562479] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 1
[   44.570366] xhci-hcd xhci-hcd.21.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   44.579876] xhci-hcd xhci-hcd.21.auto: irq 784, io mem 0x06010000
[   44.586084] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   44.591657] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 2
[   44.599395] xhci-hcd xhci-hcd.21.auto: Host supports USB 3.0 SuperSpeed
[   44.606473] hub 1-0:1.0: USB hub found
[   44.610304] hub 1-0:1.0: 1 port detected
[   44.615315] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   44.623476] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   44.623976] hub 2-0:1.0: USB hub found
[   44.631404] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   44.634752] hub 2-0:1.0: 1 port detected
[   44.651141] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   44.659311] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   44.672973] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   44.681009] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   44.689195] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   44.697639] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   44.725453] xhci-hcd xhci-hcd.21.auto: remove, state 1
[   44.730608] usb usb2: USB disconnect, device number 1
[   44.736803] xhci-hcd xhci-hcd.21.auto: USB bus 2 deregistered
[   44.742622] xhci-hcd xhci-hcd.21.auto: remove, state 84
[   44.747875] usb usb1: USB disconnect, device number 1
[   44.753588] xhci-hcd xhci-hcd.21.auto: USB bus 1 deregistered
[   44.908794] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   44.914431] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 1
[   44.922320] xhci-hcd xhci-hcd.21.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   44.931830] xhci-hcd xhci-hcd.21.auto: irq 784, io mem 0x06010000
[   44.938054] xhci-hcd xhci-hcd.21.auto: xHCI Host Controller
[   44.943628] xhci-hcd xhci-hcd.21.auto: new USB bus registered, assigned bus number 2
[   44.951366] xhci-hcd xhci-hcd.21.auto: Host supports USB 3.0 SuperSpeed
[   44.958477] hub 1-0:1.0: USB hub found
[   44.962307] hub 1-0:1.0: 1 port detected
[   44.966669] usb usb2: We don't know the algorithms for LPM for this host, disabling LPM.
[   44.974836] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   44.982500] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   44.982665] hub 2-0:1.0: USB hub found
[   44.994420] hub 2-0:1.0: 1 port detected
[   44.998853] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   45.008140] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   45.021358] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   45.031165] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   45.039401] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   45.047563] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000

root@j721s2-evm:/opt/vision_apps# 
root@j721s2-evm:/opt/vision_apps# [   47.595812] usb 1-1: new high-speed USB device number 2 using xhci-hcd
[   47.745742] usb-storage 1-1:1.0: USB Mass Storage device detected
[   47.752427] scsi host0: usb-storage 1-1:1.0
[   47.758760] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   47.766327] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   47.774466] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   47.782643] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000
[   48.779175] scsi 0:0:0:0: Direct-Access     BUFFALO  USB Flash Disk   1.00 PQ: 0 ANSI: 6
[   49.371932] sd 0:0:0:0: [sda] 60628992 512-byte logical blocks: (31.0 GB/28.9 GiB)
[   49.381169] sd 0:0:0:0: [sda] Write Protect is off
[   49.387294] sd 0:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[   49.422293]  sda: sda1
[   49.424949] sd 0:0:0:0: [sda] Attached SCSI removable disk
[   49.431866] j721e-pcie 2910000.pcie: host bridge /bus@100000/pcie@2910000 ranges:
[   49.439502] j721e-pcie 2910000.pcie:       IO 0x0018001000..0x0018010fff -> 0x0018001000
[   49.447641] j721e-pcie 2910000.pcie:      MEM 0x0018011000..0x001fffffff -> 0x0018011000
[   49.455804] j721e-pcie 2910000.pcie:   IB MEM 0x0000000000..0xffffffffffff -> 0x0000000000

    In addition, on the J721S2 EVM board, the USB 2.0 Type-A port is completely non-functional — the system does not detect any devices connected to it.

    Could you please advise how to resolve these issues or let us know if there are any known limitations?

    Best regards,
    Liu

  • 0 in reply to zemiao liu
    TI__Genius 11280 points

    Hi zemiaou,

    zemiao liu said:
    Yes, the issue I’m facing is on Linux. When I connect a USB 3.0 flash drive to the USB Type-C port (which is supposed to support USB 3.1), it only gets recognized as a USB 2.0 device both on J721E and J721S2.

    Can you share the following files which you are using :

    • k3-j721e-common-proc-board.dts
    • k3-j721e-main.dtsi

    Also can you share the SW3 setting which you are setting on the board.

    zemiao liu said:
    In addition, on the J721S2 EVM board, the USB 2.0 Type-A port is completely non-functional — the system does not detect any devices connected to it.

    This is because since J721S2 EVM has only 1 USB DRD controller at a time either C type or USB2.0 type-A port can only be enabled. 

    Hence,by default type C port is enabled.

    If you want to enable USB TYPE A port , please follow the below FAQ:

    https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1303008/faq-j721s2xsomxevm-enable-usb-2-0-hub-on-j7200-j721s2-j784s4

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 40 points

    Hi Gokul,

    Thanks for your response.

    Yes, I intend to use the USB Type-C port since I need USB 3.0 speed support.
    I will send the requested files in the next message.

    Best regards,
    Liu

  • 0 in reply to zemiao liu
    Prodigy 40 points

    Here are the files


    Fullscreen 7360.k3-j721e-common-proc-board.txt Download 
    // SPDX-License-Identifier: GPL-2.0-only OR MIT
/*
 * Copyright (C) 2019-2024 Texas Instruments Incorporated - https://www.ti.com/
 *
 * Product Link: https://www.ti.com/tool/J721EXCPXEVM
 */

/dts-v1/;

#include "k3-j721e-som-p0.dtsi"
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include <dt-bindings/net/ti-dp83867.h>
#include <dt-bindings/phy/phy-cadence.h>

/ {
	compatible = "ti,j721e-evm", "ti,j721e";
	model = "Texas Instruments J721e EVM";

	aliases {
		serial0 = &wkup_uart0;
		serial1 = &mcu_uart0;
		serial2 = &main_uart0;
		serial3 = &main_uart1;
		serial4 = &main_uart2;
		serial6 = &main_uart4;
		ethernet0 = &cpsw_port1;
		mmc0 = &main_sdhci0;
		mmc1 = &main_sdhci1;
	};

	chosen {
		stdout-path = "serial2:115200n8";
	};

	gpio_keys: gpio-keys {
		compatible = "gpio-keys";
		autorepeat;
		pinctrl-names = "default";
		pinctrl-0 = <&sw10_button_pins_default>, <&sw11_button_pins_default>;

		sw10: switch-10 {
			label = "GPIO Key USER1";
			linux,code = <BTN_0>;
			gpios = <&main_gpio0 0 GPIO_ACTIVE_LOW>;
		};

		sw11: switch-11 {
			label = "GPIO Key USER2";
			linux,code = <BTN_1>;
			gpios = <&wkup_gpio0 7 GPIO_ACTIVE_LOW>;
		};
	};

	evm_12v0: fixedregulator-evm12v0 {
		/* main supply */
		compatible = "regulator-fixed";
		regulator-name = "evm_12v0";
		regulator-min-microvolt = <12000000>;
		regulator-max-microvolt = <12000000>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_3v3: fixedregulator-vsys3v3 {
		/* Output of LMS140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_3v3";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vsys_5v0: fixedregulator-vsys5v0 {
		/* Output of LM5140 */
		compatible = "regulator-fixed";
		regulator-name = "vsys_5v0";
		regulator-min-microvolt = <5000000>;
		regulator-max-microvolt = <5000000>;
		vin-supply = <&evm_12v0>;
		regulator-always-on;
		regulator-boot-on;
	};

	vdd_mmc1: fixedregulator-sd {
		compatible = "regulator-fixed";
		regulator-name = "vdd_mmc1";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		enable-active-high;
		vin-supply = <&vsys_3v3>;
		gpio = <&exp2 2 GPIO_ACTIVE_HIGH>;
	};

	vdd_sd_dv_alt: gpio-regulator-TLV71033 {
		compatible = "regulator-gpio";
		pinctrl-names = "default";
		pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
		regulator-name = "tlv71033";
		regulator-min-microvolt = <1800000>;
		regulator-max-microvolt = <3300000>;
		regulator-boot-on;
		vin-supply = <&vsys_5v0>;
		gpios = <&main_gpio0 117 GPIO_ACTIVE_HIGH>;
		states = <1800000 0x0>,
			 <3300000 0x1>;
	};

	sound0: sound-0 {
		compatible = "ti,j721e-cpb-audio";
		model = "j721e-cpb";

		ti,cpb-mcasp = <&mcasp10>;
		ti,cpb-codec = <&pcm3168a_1>;

		clocks = <&k3_clks 184 1>,
			 <&k3_clks 184 2>, <&k3_clks 184 4>,
			 <&k3_clks 157 371>,
			 <&k3_clks 157 400>, <&k3_clks 157 401>;
		clock-names = "cpb-mcasp-auxclk",
			      "cpb-mcasp-auxclk-48000", "cpb-mcasp-auxclk-44100",
			      "cpb-codec-scki",
			      "cpb-codec-scki-48000", "cpb-codec-scki-44100";
	};

	transceiver1: can-phy0 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan0_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 54 GPIO_ACTIVE_LOW>;
		enable-gpios = <&wkup_gpio0 0 GPIO_ACTIVE_HIGH>;
	};

	transceiver2: can-phy1 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&mcu_mcan1_gpio_pins_default>;
		standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>;
	};

	transceiver3: can-phy2 {
		compatible = "ti,tcan1043";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		standby-gpios = <&exp2 7 GPIO_ACTIVE_LOW>;
		enable-gpios = <&exp2 6 GPIO_ACTIVE_HIGH>;
	};

	transceiver4: can-phy3 {
		compatible = "ti,tcan1042";
		#phy-cells = <0>;
		max-bitrate = <5000000>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_mcan2_gpio_pins_default>;
		standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>;
	};

	dp_pwr_3v3: regulator-dp-pwr {
		compatible = "regulator-fixed";
		regulator-name = "dp-pwr";
		regulator-min-microvolt = <3300000>;
		regulator-max-microvolt = <3300000>;
		gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; /* P0 - DP0_PWR_SW_EN */
		enable-active-high;
	};

	dp0: connector {
		compatible = "dp-connector";
		label = "DP0";
		type = "full-size";
		dp-pwr-supply = <&dp_pwr_3v3>;

		port {
			dp_connector_in: endpoint {
				remote-endpoint = <&dp0_out>;
			};
		};
	};
};

&main_pmx0 {
	main_uart0_pins_default: main-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d4, PIN_INPUT, 1) /* (Y3) SPI1_CS0.UART0_CTSn */
			J721E_IOPAD(0x1c0, PIN_OUTPUT, 1) /* (AA2) SPI0_CS0.UART0_RTSn */
			J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
			J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
		>;
	};

	main_uart1_pins_default: main-uart1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1f8, PIN_INPUT, 0) /* (AA4) UART1_RXD */
			J721E_IOPAD(0x1fc, PIN_OUTPUT, 0) /* (AB4) UART1_TXD */
		>;
	};

	main_uart2_pins_default: main-uart2-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1dc, PIN_INPUT, 3) /* (Y1) SPI1_CLK.UART2_RXD */
			J721E_IOPAD(0x1e0, PIN_OUTPUT, 3) /* (Y5) SPI1_D0.UART2_TXD */
		>;
	};

	main_uart4_pins_default: main-uart4-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x190, PIN_INPUT, 1) /* (W23) RGMII6_TD3.UART4_RXD */
			J721E_IOPAD(0x194, PIN_OUTPUT, 1) /* (W28) RGMII6_TD2.UART4_TXD */
		>;
	};

	sw10_button_pins_default: sw10-button-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x0, PIN_INPUT, 7) /* (AC18) EXTINTn.GPIO0_0 */
		>;
	};

	main_mmc1_pins_default: main-mmc1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
			J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
			J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
			J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
			J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
			J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
			J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
			J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
			J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
		>;
	};

	vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d8, PIN_INPUT, 7) /* (W4) SPI1_CS1.GPIO0_117 */
		>;
	};

	main_usbss0_pins_default: main-usbss0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
			J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
		>;
	};

	main_usbss1_pins_default: main-usbss1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
		>;
	};

	dp0_pins_default: dp0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */
		>;
	};

	main_i2c1_exp4_pins_default: main-i2c1-exp4-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */
		>;
	};

	main_i2c0_pins_default: main-i2c0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
			J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
		>;
	};

	main_i2c1_pins_default: main-i2c1-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
			J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
		>;
	};

	main_i2c3_pins_default: main-i2c3-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
			J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
		>;
	};

	main_i2c6_pins_default: main-i2c6-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1d0, PIN_INPUT_PULLUP, 2) /* (AA3) SPI0_D1.I2C6_SCL */
			J721E_IOPAD(0x1e4, PIN_INPUT_PULLUP, 2) /* (Y2) SPI1_D1.I2C6_SDA */
		>;
	};

	mcasp10_pins_default: mcasp10-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x158, PIN_OUTPUT_PULLDOWN, 12) /* (U23) RGMII5_TX_CTL.MCASP10_ACLKX */
			J721E_IOPAD(0x15c, PIN_OUTPUT_PULLDOWN, 12) /* (U26) RGMII5_RX_CTL.MCASP10_AFSX */
			J721E_IOPAD(0x160, PIN_OUTPUT_PULLDOWN, 12) /* (V28) RGMII5_TD3.MCASP10_AXR0 */
			J721E_IOPAD(0x164, PIN_OUTPUT_PULLDOWN, 12) /* (V29) RGMII5_TD2.MCASP10_AXR1 */
			J721E_IOPAD(0x170, PIN_OUTPUT_PULLDOWN, 12) /* (U29) RGMII5_TXC.MCASP10_AXR2 */
			J721E_IOPAD(0x174, PIN_OUTPUT_PULLDOWN, 12) /* (U25) RGMII5_RXC.MCASP10_AXR3 */
			J721E_IOPAD(0x198, PIN_INPUT_PULLDOWN, 12) /* (V25) RGMII6_TD1.MCASP10_AXR4 */
			J721E_IOPAD(0x19c, PIN_INPUT_PULLDOWN, 12) /* (W27) RGMII6_TD0.MCASP10_AXR5 */
			J721E_IOPAD(0x1a0, PIN_INPUT_PULLDOWN, 12) /* (W29) RGMII6_TXC.MCASP10_AXR6 */
		>;
	};

	audi_ext_refclk2_pins_default: audi-ext-refclk2-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x1a4, PIN_OUTPUT, 3) /* (W26) RGMII6_RXC.AUDIO_EXT_REFCLK2 */
		>;
	};

	main_mcan0_pins_default: main-mcan0-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x208, PIN_INPUT, 0) /* (W5) MCAN0_RX */
			J721E_IOPAD(0x20c, PIN_OUTPUT, 0) /* (W6) MCAN0_TX */
		>;
	};

	main_mcan2_pins_default: main-mcan2-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x01f0, PIN_INPUT, 3) /* (AC2) MCAN2_RX.GPIO0_123 */
			J721E_IOPAD(0x01f4, PIN_OUTPUT, 3) /* (AB1) MCAN2_TX.GPIO0_124 */
		>;
	};

	main_mcan2_gpio_pins_default: main-mcan2-gpio-default-pins {
		pinctrl-single,pins = <
			J721E_IOPAD(0x200, PIN_INPUT, 7) /* (AC4) UART1_CTSn.GPIO0_127 */
		>;
	};
};

&wkup_pmx0 {
	wkup_uart0_pins_default: wkup-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xa0, PIN_INPUT, 0) /* (J29) WKUP_UART0_RXD */
			J721E_WKUP_IOPAD(0xa4, PIN_OUTPUT, 0) /* (J28) WKUP_UART0_TXD */
		>;
	};

	mcu_uart0_pins_default: mcu-uart0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xe8, PIN_INPUT, 0) /* (H29) WKUP_GPIO0_14.MCU_UART0_CTSn */
			J721E_WKUP_IOPAD(0xec, PIN_OUTPUT, 0) /* (J27) WKUP_GPIO0_15.MCU_UART0_RTSn */
			J721E_WKUP_IOPAD(0xe4, PIN_INPUT, 0) /* (H28) WKUP_GPIO0_13.MCU_UART0_RXD */
			J721E_WKUP_IOPAD(0xe0, PIN_OUTPUT, 0) /* (G29) WKUP_GPIO0_12.MCU_UART0_TXD */
		>;
	};

	sw11_button_pins_default: sw11-button-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xcc, PIN_INPUT, 7) /* (G28) WKUP_GPIO0_7 */
		>;
	};

	mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x34, PIN_OUTPUT, 0) /* (F22) MCU_OSPI1_CLK */
			J721E_WKUP_IOPAD(0x50, PIN_OUTPUT, 0) /* (C22) MCU_OSPI1_CSn0 */
			J721E_WKUP_IOPAD(0x40, PIN_INPUT, 0) /* (D22) MCU_OSPI1_D0 */
			J721E_WKUP_IOPAD(0x44, PIN_INPUT, 0) /* (G22) MCU_OSPI1_D1 */
			J721E_WKUP_IOPAD(0x48, PIN_INPUT, 0) /* (D23) MCU_OSPI1_D2 */
			J721E_WKUP_IOPAD(0x4c, PIN_INPUT, 0) /* (C23) MCU_OSPI1_D3 */
			J721E_WKUP_IOPAD(0x3c, PIN_INPUT, 0) /* (B23) MCU_OSPI1_DQS */
			J721E_WKUP_IOPAD(0x38, PIN_INPUT, 0) /* (A23) MCU_OSPI1_LBCLKO */
		>;
	};

	mcu_cpsw_pins_default: mcu-cpsw-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x0058, PIN_OUTPUT, 0) /* MCU_RGMII1_TX_CTL */
			J721E_WKUP_IOPAD(0x005c, PIN_INPUT, 0) /* MCU_RGMII1_RX_CTL */
			J721E_WKUP_IOPAD(0x0060, PIN_OUTPUT, 0) /* MCU_RGMII1_TD3 */
			J721E_WKUP_IOPAD(0x0064, PIN_OUTPUT, 0) /* MCU_RGMII1_TD2 */
			J721E_WKUP_IOPAD(0x0068, PIN_OUTPUT, 0) /* MCU_RGMII1_TD1 */
			J721E_WKUP_IOPAD(0x006c, PIN_OUTPUT, 0) /* MCU_RGMII1_TD0 */
			J721E_WKUP_IOPAD(0x0078, PIN_INPUT, 0) /* MCU_RGMII1_RD3 */
			J721E_WKUP_IOPAD(0x007c, PIN_INPUT, 0) /* MCU_RGMII1_RD2 */
			J721E_WKUP_IOPAD(0x0080, PIN_INPUT, 0) /* MCU_RGMII1_RD1 */
			J721E_WKUP_IOPAD(0x0084, PIN_INPUT, 0) /* MCU_RGMII1_RD0 */
			J721E_WKUP_IOPAD(0x0070, PIN_OUTPUT, 0) /* MCU_RGMII1_TXC */
			J721E_WKUP_IOPAD(0x0074, PIN_INPUT, 0) /* MCU_RGMII1_RXC */
		>;
	};

	mcu_mdio_pins_default: mcu-mdio1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0x008c, PIN_OUTPUT, 0) /* MCU_MDIO0_MDC */
			J721E_WKUP_IOPAD(0x0088, PIN_INPUT, 0) /* MCU_MDIO0_MDIO */
		>;
	};

	mcu_mcan0_pins_default: mcu-mcan0-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xac, PIN_INPUT, 0) /* (C29) MCU_MCAN0_RX */
			J721E_WKUP_IOPAD(0xa8, PIN_OUTPUT, 0) /* (D29) MCU_MCAN0_TX */
		>;
	};

	mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb0, PIN_INPUT, 7) /* (F26) WKUP_GPIO0_0 */
			J721E_WKUP_IOPAD(0x98, PIN_INPUT, 7) /* (E28) MCU_SPI0_D1.WKUP_GPIO0_54 */
		>;
	};

	mcu_mcan1_pins_default: mcu-mcan1-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xc4, PIN_INPUT, 0) /* (G24) WKUP_GPIO0_5.MCU_MCAN1_RX */
			J721E_WKUP_IOPAD(0xc0, PIN_OUTPUT, 0) /* (G25) WKUP_GPIO0_4.MCU_MCAN1_TX */
		>;
	};

	mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xb8, PIN_INPUT, 7) /* (F28) WKUP_GPIO0_2 */
		>;
	};

	wkup_gpio_pins_default: wkup-gpio-default-pins {
		pinctrl-single,pins = <
			J721E_WKUP_IOPAD(0xd0, PIN_INPUT, 7) /* (C14) WKUP_GPIO0_8 */
		>;
	};
};

&wkup_uart0 {
	/* Wakeup UART is used by System firmware */
	status = "reserved";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_uart0_pins_default>;
};

&mcu_uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_uart0_pins_default>;
};

&main_uart0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart0_pins_default>;
	/* Shared with ATF on this platform */
	power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
};

&main_uart1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart1_pins_default>;
};

&main_uart2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart2_pins_default>;
};

&main_uart4 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_uart4_pins_default>;
};

&wkup_gpio0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&wkup_gpio_pins_default>;
};

&main_gpio0 {
	status = "okay";
};

&main_gpio1 {
	status = "okay";
};

&main_sdhci0 {
	/* eMMC */
	status = "okay";
	non-removable;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&main_sdhci1 {
	/* SD/MMC */
	status = "okay";
	vmmc-supply = <&vdd_mmc1>;
	vqmmc-supply = <&vdd_sd_dv_alt>;
	pinctrl-names = "default";
	pinctrl-0 = <&main_mmc1_pins_default>;
	ti,driver-strength-ohm = <50>;
	disable-wp;
};

&usb_serdes_mux {
	idle-states = <1>, <0>; /* USB0 to SERDES3, USB1 to SERDES1 */
};

&serdes_ln_ctrl {
	idle-states = <J721E_SERDES0_LANE0_PCIE0_LANE0>, <J721E_SERDES0_LANE1_PCIE0_LANE1>,
		      <J721E_SERDES1_LANE0_PCIE1_LANE0>, <J721E_SERDES1_LANE1_PCIE1_LANE1>,
		      <J721E_SERDES2_LANE0_PCIE2_LANE0>, <J721E_SERDES2_LANE1_PCIE2_LANE1>,
		      <J721E_SERDES3_LANE0_USB3_0_SWAP>, <J721E_SERDES3_LANE1_USB3_0>,
		      <J721E_SERDES4_LANE0_EDP_LANE0>, <J721E_SERDES4_LANE1_EDP_LANE1>,
		      <J721E_SERDES4_LANE2_EDP_LANE2>, <J721E_SERDES4_LANE3_EDP_LANE3>;
};

&serdes_wiz3 {
	typec-dir-gpios = <&main_gpio1 3 GPIO_ACTIVE_HIGH>;
	typec-dir-debounce-ms = <700>;	/* TUSB321, tCCB_DEFAULT 133 ms */
};

&serdes3 {
	serdes3_usb_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_USB3>;
		resets = <&serdes_wiz3 1>, <&serdes_wiz3 2>;
	};
};

&usbss0 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss0_pins_default>;
	ti,vbus-divider;
};

&usb0 {
	dr_mode = "otg";
	maximum-speed = "super-speed";
	phys = <&serdes3_usb_link>;
	phy-names = "cdns3,usb3-phy";
};

&usbss1 {
	pinctrl-names = "default";
	pinctrl-0 = <&main_usbss1_pins_default>;
	ti,usb2-only;
};

&usb1 {
	dr_mode = "host";
	maximum-speed = "high-speed";
};

&ospi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "qspi.tiboot3";
				reg = <0x0 0x80000>;
			};

			partition@80000 {
				label = "qspi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "qspi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "qspi.env";
				reg = <0x680000 0x20000>;
			};

			partition@6a0000 {
				label = "qspi.env.backup";
				reg = <0x6a0000 0x20000>;
			};

			partition@6c0000 {
				label = "qspi.sysfw";
				reg = <0x6c0000 0x100000>;
			};

			partition@800000 {
				label = "qspi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fe0000 {
				label = "qspi.phypattern";
				reg = <0x3fe0000 0x20000>;
			};
		};
	};
};

&tscadc0 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&tscadc1 {
	status = "okay";
	adc {
		ti,adc-channels = <0 1 2 3 4 5 6 7>;
	};
};

&main_i2c0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c0_pins_default>;
	clock-frequency = <400000>;

	exp1: gpio@20 {
		compatible = "ti,tca6416";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	exp2: gpio@22 {
		compatible = "ti,tca6424";
		reg = <0x22>;
		gpio-controller;
		#gpio-cells = <2>;

		p09-hog {
			/* P11 - MCASP/TRACE_MUX_S0 */
			gpio-hog;
			gpios = <9 GPIO_ACTIVE_HIGH>;
			output-low;
			line-name = "MCASP/TRACE_MUX_S0";
		};

		p10-hog {
			/* P12 - MCASP/TRACE_MUX_S1 */
			gpio-hog;
			gpios = <10 GPIO_ACTIVE_HIGH>;
			output-high;
			line-name = "MCASP/TRACE_MUX_S1";
		};
	};
};

&main_i2c1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c1_pins_default>;
	clock-frequency = <400000>;

	exp4: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
		pinctrl-names = "default";
		pinctrl-0 = <&main_i2c1_exp4_pins_default>;
		interrupt-parent = <&main_gpio1>;
		interrupts = <11 IRQ_TYPE_EDGE_FALLING>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};
};

&k3_clks {
	/* Confiure AUDIO_EXT_REFCLK2 pin as output */
	pinctrl-names = "default";
	pinctrl-0 = <&audi_ext_refclk2_pins_default>;
};

&main_i2c3 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c3_pins_default>;
	clock-frequency = <400000>;

	exp3: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};

	pcm3168a_1: audio-codec@44 {
		compatible = "ti,pcm3168a";
		reg = <0x44>;

		#sound-dai-cells = <1>;

		reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>;

		/* C_AUDIO_REFCLK2 -> RGMII6_RXC (W26) */
		clocks = <&k3_clks 157 371>;
		clock-names = "scki";

		/* HSDIV3_16FFT_MAIN_4_HSDIVOUT2_CLK -> REFCLK2 */
		assigned-clocks = <&k3_clks 157 371>;
		assigned-clock-parents = <&k3_clks 157 400>;
		assigned-clock-rates = <24576000>; /* for 48KHz */

		VDD1-supply = <&vsys_3v3>;
		VDD2-supply = <&vsys_3v3>;
		VCCAD1-supply = <&vsys_5v0>;
		VCCAD2-supply = <&vsys_5v0>;
		VCCDA1-supply = <&vsys_5v0>;
		VCCDA2-supply = <&vsys_5v0>;
	};
};

&main_i2c6 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_i2c6_pins_default>;
	clock-frequency = <400000>;

	exp5: gpio@20 {
		compatible = "ti,tca6408";
		reg = <0x20>;
		gpio-controller;
		#gpio-cells = <2>;
	};
};

&mcu_cpsw {
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>;

	cpts@3d000 {
		/* Map HW4_TS_PUSH to GENF1 */
		ti,pps = <3 1>;
	};
};

&davinci_mdio {
	phy0: ethernet-phy@0 {
		reg = <0>;
		ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
		ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
	};
};

&cpsw_port1 {
	phy-mode = "rgmii-rxid";
	phy-handle = <&phy0>;
};

&dss {
	/*
	 * These clock assignments are chosen to enable the following outputs:
	 *
	 * VP0 - DisplayPort SST
	 * VP1 - DPI0
	 * VP2 - DSI
	 * VP3 - DPI1
	 */

	assigned-clocks = <&k3_clks 152 1>,
			  <&k3_clks 152 4>,
			  <&k3_clks 152 9>,
			  <&k3_clks 152 13>;
	assigned-clock-parents = <&k3_clks 152 2>,	/* PLL16_HSDIV0 */
				 <&k3_clks 152 6>,	/* PLL19_HSDIV0 */
				 <&k3_clks 152 11>,	/* PLL18_HSDIV0 */
				 <&k3_clks 152 18>;	/* PLL23_HSDIV0 */
};

&dss_ports {
	port {
		dpi0_out: endpoint {
			remote-endpoint = <&dp0_in>;
		};
	};
};

&dp0_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;
		dp0_in: endpoint {
			remote-endpoint = <&dpi0_out>;
		};
	};

	port@4 {
		reg = <4>;
		dp0_out: endpoint {
			remote-endpoint = <&dp_connector_in>;
		};
	};
};

&mcasp10 {
	status = "okay";
	#sound-dai-cells = <0>;

	pinctrl-names = "default";
	pinctrl-0 = <&mcasp10_pins_default>;

	op-mode = <0>;          /* MCASP_IIS_MODE */
	tdm-slots = <2>;
	auxclk-fs-ratio = <256>;

	serial-dir = <	/* 0: INACTIVE, 1: TX, 2: RX */
		1 1 1 1
		2 2 2 0
	>;
	tx-num-evt = <0>;
	rx-num-evt = <0>;
};

&cmn_refclk1 {
	clock-frequency = <100000000>;
};

&wiz0_pll1_refclk {
	assigned-clocks = <&wiz0_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz0_refclk_dig {
	assigned-clocks = <&wiz0_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_pll1_refclk {
	assigned-clocks = <&wiz1_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz1_refclk_dig {
	assigned-clocks = <&wiz1_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_pll1_refclk {
	assigned-clocks = <&wiz2_pll1_refclk>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&wiz2_refclk_dig {
	assigned-clocks = <&wiz2_refclk_dig>;
	assigned-clock-parents = <&cmn_refclk1>;
};

&serdes0 {
	assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz0_pll1_refclk>;

	serdes0_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <1>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz0 1>;
	};
};

&serdes1 {
	assigned-clocks = <&serdes1 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz1_pll1_refclk>;

	serdes1_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>;
	};
};

&serdes2 {
	assigned-clocks = <&serdes2 CDNS_SIERRA_PLL_CMNLC>;
	assigned-clock-parents = <&wiz2_pll1_refclk>;

	serdes2_pcie_link: phy@0 {
		reg = <0>;
		cdns,num-lanes = <2>;
		#phy-cells = <0>;
		cdns,phy-type = <PHY_TYPE_PCIE>;
		resets = <&serdes_wiz2 1>, <&serdes_wiz2 2>;
	};
};

&serdes4 {
	torrent_phy_dp: phy@0 {
		reg = <0>;
		resets = <&serdes_wiz4 1>;
		cdns,phy-type = <PHY_TYPE_DP>;
		cdns,num-lanes = <4>;
		cdns,max-bit-rate = <2700>;
		#phy-cells = <0>;
	};
};

&mhdp {
	phys = <&torrent_phy_dp>;
	phy-names = "dpphy";
	pinctrl-names = "default";
	pinctrl-0 = <&dp0_pins_default>;
};

&pcie0_rc {
	status = "okay";
	reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>;
	phys = <&serdes0_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <1>;
};

&pcie1_rc {
	status = "okay";
	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
	phys = <&serdes1_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

&pcie2_rc {
	status = "okay";
	reset-gpios = <&exp2 20 GPIO_ACTIVE_HIGH>;
	phys = <&serdes2_pcie_link>;
	phy-names = "pcie-phy";
	num-lanes = <2>;
};

&mcu_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan0_pins_default>;
	phys = <&transceiver1>;
};

&mcu_mcan1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_mcan1_pins_default>;
	phys = <&transceiver2>;
};

&main_mcan0 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan0_pins_default>;
	phys = <&transceiver3>;
};

&main_mcan2 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_mcan2_pins_default>;
	phys = <&transceiver4>;
};

#define K3_TS_OFFSET(pa, val)	(0x4+(pa)*4) (0x10000 | val)

&timesync_router {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_cpsw_cpts>;

	/* Use Time Sync Router to map GENF1 input to HW4_TS_PUSH output */
	mcu_cpsw_cpts: mcu-cpsw-cpts {
		pinctrl-single,pins = <
			/* pps [mcu cpsw cpts genf1] in17 -> out25 [mcu cpsw cpts hw4_push] */
			K3_TS_OFFSET(25, 17)
			>;
	};
};

    k3-j721e-main.txt

  • 0 in reply to zemiao liu
    TI__Genius 11280 points

    Hi Zemiao,

    Can you make the following changes:

    • Can you change to dr_mode="host" in k3-j721e-common-proc-board.dts.

    • Can you change to dr_mode="host" in k3-j721e-main.dtsi.

    • Can you ensure SW3.3=0 and SW3.4=0.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 40 points

    Hi Gokul,

    Thanks for the support.
    I’ve updated the Device Tree with dr_mode = "host" and rebuilt the DTB successfully.
    After booting, I confirmed via /proc/device-tree that the dr_mode is correctly set to host.

    root@j721e-evm:/# strings /proc/device-tree/bus@100000/cdns-usb@4104000/usb@6000000/dr_mode
host

    Also, I’ve set SW3.3 = 0 and SW3.4 = 0 as suggested.

    However, when I connect a USB 3.0 flash drive to the USB Type-C port, it still gets
    recognized as a USB 2.0 device (High-Speed).
    So unfortunately, the issue still persists.

    [11482.995635] usb 1-1: new high-speed USB device number 4 using xhci-hcd
[11483.160656] usb-storage 1-1:1.0: USB Mass Storage device detected
[11483.171097] scsi host1: usb-storage 1-1:1.0
[11484.210901] scsi 1:0:0:0: Direct-Access     BUFFALO  USB Flash Disk   1.00 PQ: 0 ANSI: 6
[11484.773237] sd 1:0:0:0: [sda] 60628992 512-byte logical blocks: (31.0 GB/28.9 GiB)
[11484.782442] sd 1:0:0:0: [sda] Write Protect is off
[11484.788568] sd 1:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[11484.804556]  sda: sda1
[11484.807127] sd 1:0:0:0: [sda] Attached SCSI removable disk

root@j721e-evm:~# lsusb -t
/:  Bus 001.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 480M
    |__ Port 001: Dev 004, If 0, Class=Mass Storage, Driver=usb-storage, 480M
/:  Bus 002.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 5000M
/:  Bus 003.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 480M
    |__ Port 001: Dev 002, If 0, Class=Hub, Driver=hub/4p, 480M
/:  Bus 004.Port 001: Dev 001, Class=root_hub, Driver=xhci-hcd/1p, 5000M

    Please let me know if there are any other points I should check.

    Best regards,
    Liu

  • 0 in reply to zemiao liu
    TI__Genius 11280 points

    Hi zemiaou,

    Can you try with the below dtb for j721e as it was working for me:

    https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_j721e_2D00_common_2D00_proc_2D00_board.dtb

    Logs:

    Also,just to confirm,you are using j721e 10.01.04 linux sdk version right?

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 40 points

    Hi Gokul,

    Thanks for sharing the .dtb file.

    I just tested it on my J721E board, but unfortunately the USB device is still detected as high-speed (USB 2.0) rather than super-speed (USB 3.0).
    The log does show Host supports USB 3.0 SuperSpeed, so the controller seems to be recognized correctly, but the enumeration still ends up as USB 2.0.

    Here are the logs.

    root@j721e-evm:~# [   64.770557] xhci-hcd xhci-hcd.20.auto: xHCI Host Controller
[   64.776175] xhci-hcd xhci-hcd.20.auto: new USB bus registered, assigned bus number 3
[   64.784356] xhci-hcd xhci-hcd.20.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   64.793859] xhci-hcd xhci-hcd.20.auto: irq 861, io mem 0x06010000
[   64.800046] xhci-hcd xhci-hcd.20.auto: xHCI Host Controller
[   64.805613] xhci-hcd xhci-hcd.20.auto: new USB bus registered, assigned bus number 4
[   64.813345] xhci-hcd xhci-hcd.20.auto: Host supports USB 3.0 SuperSpeed
[   64.820323] hub 3-0:1.0: USB hub found
[   64.824117] hub 3-0:1.0: 1 port detected
[   64.828328] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
[   64.836856] hub 4-0:1.0: USB hub found
[   64.840683] hub 4-0:1.0: 1 port detected
[   64.926023] xhci-hcd xhci-hcd.20.auto: remove, state 1
[   64.931175] usb usb4: USB disconnect, device number 1
[   64.937094] xhci-hcd xhci-hcd.20.auto: USB bus 4 deregistered
[   64.942873] xhci-hcd xhci-hcd.20.auto: remove, state 84
[   64.948114] usb usb3: USB disconnect, device number 1
[   64.954601] xhci-hcd xhci-hcd.20.auto: USB bus 3 deregistered
[   65.826508] xhci-hcd xhci-hcd.20.auto: xHCI Host Controller
[   65.832093] xhci-hcd xhci-hcd.20.auto: new USB bus registered, assigned bus number 3
[   65.840260] xhci-hcd xhci-hcd.20.auto: hcc params 0x200073c9 hci version 0x100 quirks 0x0000002000008010
[   65.849748] xhci-hcd xhci-hcd.20.auto: irq 861, io mem 0x06010000
[   65.855922] xhci-hcd xhci-hcd.20.auto: xHCI Host Controller
[   65.861488] xhci-hcd xhci-hcd.20.auto: new USB bus registered, assigned bus number 4
[   65.869220] xhci-hcd xhci-hcd.20.auto: Host supports USB 3.0 SuperSpeed
[   65.876187] hub 3-0:1.0: USB hub found
[   65.879954] hub 3-0:1.0: 1 port detected
[   65.884563] usb usb4: We don't know the algorithms for LPM for this host, disabling LPM.
[   65.893146] hub 4-0:1.0: USB hub found
[   65.896964] hub 4-0:1.0: 1 port detected
[   68.322246] usb 3-1: new high-speed USB device number 2 using xhci-hcd
[   68.484043] usb-storage 3-1:1.0: USB Mass Storage device detected
[   68.490855] scsi host1: usb-storage 3-1:1.0
[   69.509570] scsi 1:0:0:0: Direct-Access     BUFFALO  USB Flash Disk   1.00 PQ: 0 ANSI: 6
[   69.880221] sd 1:0:0:0: [sda] 60628992 512-byte logical blocks: (31.0 GB/28.9 GiB)
[   69.889383] sd 1:0:0:0: [sda] Write Protect is off
[   69.895517] sd 1:0:0:0: [sda] Write cache: disabled, read cache: enabled, doesn't support DPO or FUA
[   69.913182]  sda: sda1
[   69.915757] sd 1:0:0:0: [sda] Attached SCSI removable disk

    And yes, I can confirm that I’m using J721E Linux SDK version 10.01.04.



    If there are any other suggestions or checks I can try, please let me know.

    Best regards,
    Liu

  • 0 in reply to zemiao liu
    TI__Genius 11280 points

    Hi zemiaou,

    Just to confirm, you are using the default kernel Image and rootfs from the SDK itself right or have you made any changes to it.

    Regards

    Gokul

  • 0 in reply to Gokul Praveen
    Prodigy 40 points

    Hi Gokul,

    Yes, I’m using the default Image and rootfs from the SDK 10.01.00.04 package, without any modifications.

    Best regards,
    Liu

  • 0 in reply to zemiao liu
    TI__Genius 11280 points

    HI Zemiao,

    I will look into this and get back to you.

    Regards

    Gokul