AM623: DDR delay register configuration

Hi James,

This is a reminder for response.

Regards

Ashwani

Hi James,

A reminder for response.

Regards

Ashwani

James is out of office until 16-Sep.

Regards

Ashwani

sorry for the long delay here.  I'm assuming you are not blocked, so there have been higher priority issues i have been working on.  Still need to look into this.. 

Regards,

James

I did some investigation, and I believe CL needs to be set to 14 in the case.  So a working configuration is:

DDRSS.ddr4.config_dram_mr0_cl = 14;

DDRSS.ddr4.config_dram_mr2_cwl = 9;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "4 clocks";

The JEDEC spec indicates this in the rounding algorithms section with tAA_DBI = 13.32 + 3tCK

CL = CEILING(tAA/tCK) - 0.025)

Regards,

James

Hi James

  Now that the CL should be set to 14, I don't doubt your result,   but actually our device  can not boot when set CL 14,  So base on your experience, what may be causing the issue?

Can you try with CWL = 11.

Also, please send the full config (.sysconfig and .dtsi) with CL=14 that isn't working.  I will check

Regards,

James

Hi James

   verify again, cl 14 and cwl 9 can boot normally, thanks very much 

Ok, i will close the thread.

Thanks,

James