AM623: DDR delay register configuration

Hi Kris, can you please provide the specific DDR you are using?  Also, have you used the DDR register configuration tool https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM62x to configure the DDR Subsystem for your specific DDR and board?  If so, please provide the resulting files (.dtsi or .h, and .syscfg) that were generated and are using in your code build.

Regards,

James

Hi James

Thank you for the prompt response.

Could you please share your email address so that I can sent you the datasheet ? the MPN of the DDR is :

ISSI-43-46QR85120B-16256B

For the SW part I'm confirming with team, will come back when I got the answer.

Thanks!

Hi Kris, part number is enough, i can look that up on the web.  Please provide software files when you get them.

James

Hi James, I ran into some issue in uploading the files here.

I sent a mail to Zekun and asked his help to send them to you.

Could you please help check your mailbox?

Many thanks!

Hi James

PFA, Thanks for support as always.

https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0081.k3_2D00_am62x_2D00_ddr_2D00_config.dtsihttps://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/0081.settings_5F00_info.syscfg

Regards

Zekun

Are you using  512Mbx8 or 256Mbx16?  I'm assuming you are using the x16 device.  And what speed grade device are you using?  

You have set CL=17 and CWL=12, but for the operating frequency you are running, it should be CL=14 (or 13), CWL=11 (or 9).  CA parity latency should be 4 clocks for 1600MTs.  And if you are operating at 95C, tREFI needs to be 3900ns (the tool automatically changes this when you change the operating temperature.  Also, where did you get tRCD = 14.16ns.

Maybe the datasheet on the web is not appropriate.  Please post the datasheet you are using.

Regards,

James

ISSI-43-46QR85120B-16256B-（三星替代）(1).pdf

we are using IS43QR16256B-083RBLI the 256MB*16 model, the data speed is 2400.

That datasheet looks the same, so all of the above comments apply.  You need to make those changes, and maybe other.  Please review all of the parameters in the tool.  If you have further questions, let me know.

Regards,

James

hi JJD

  the IS43QR16256B-083RBLI   data speed is 2400 , but am623 only support 1600.   do you mean we should select  the 1600 parameters  from DDR4 datasheet  for all Sysconfig  required ? 

I adjust the parameter as 1600 data rate for sysconfig, and attatch syscfg and dtsi files to following docx file, 

but system can not startup and block in uboot, please help check

sysconfig-1600.docx 

bootlog:

Hi,

it appears that the bootlog shows that you are successfully getting through DDR initialization now, but you are hanging trying to boot from your NAND device.  So now this is a completely different problem.  

How did you program the NAND device?  Can you give details on what device it is any how you configured it in the device tree?

Regards,

James

Hi JJD

 I don't  think it is NAND issue,   I didn‘t  do any other changed other than DDR configuration ,  I only change the k3-am62x-ddr-config.dtsi file , if I restore the  k3-am62x-ddr-config.dtsi file to early version , system can boot normally , please help check again, thanks

Can you try loading the attached file into the Sysconfig DDR tool and running with the generated config.  I commented out some of the lines to reduce the number of variables.

/cfs-file/__key/communityserver-discussions-components-files/791/settings_5F00_info_5F00_TIchanges.syscfg

Can you also send the .dtsi file that works?  Is it the default file in the SDK?

Regards,

James

hi  James

  I have tried your syscfg file,  still can't work, will block in uboot

Can you also send the .dtsi file that works?  Is it the default file in the SDK?

 I have attach the syscfg and dtsi file that are work  in following docx file, please check.  I configure it base on DDR4-2400 data speed , not the default file in the sdk

syscfg-base-on-2400.docx

Can you try with the attached file, which is the DDR4-1600 configuration, but I changed CWL=11, and CA Parity Latency disabled

/cfs-file/__key/communityserver-discussions-components-files/791/k3_2D00_am62x_2D00_ddr_2D00_config_5F00_CWL11.dtsi

Regards,

James

hi  James

  I have tried CWL 11 dtsi file,  ,  but still can't work, will block in uboot

Hi Bert, I'm not sure why the 1600 configuration doesn't work for you.  I've been comparing the two, and the only things that i think would make a big difference are the following changes:

DDRSS.ddr4.config_dram_mr0_cl = 13;
DDRSS.ddr4.config_dram_mr2_cwl = 9;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "4 clocks";

If you could change these one by one, back to what you have for 2400 configuration, then i might be able to explain what is going on.  

Regards,

James

hi  James

  As you predicted,  after restore cl/cwl/ca_par_lat value same to  2400 configuration  for 1600 configuration,  system can boot normally .

please help explain the reason , is it maybe hardware layout issue ? 

DDRSS.ddr4.config_dram_mr0_cl = 17;
DDRSS.ddr4.config_dram_mr2_cwl = 12;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "5 clocks";

did you restore all of them at the same time?  If so, can you try to change one by one?  That will help narrow down the issue.  Can you try the following combinations:

DDRSS.ddr4.config_dram_mr0_cl = 13;
DDRSS.ddr4.config_dram_mr2_cwl = 12;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "5 clocks";

DDRSS.ddr4.config_dram_mr0_cl = 13;
DDRSS.ddr4.config_dram_mr2_cwl = 9;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "5 clocks";

Regards,

James

hi  James:

below combinations(cwl=12) can boot normally

DDRSS.ddr4.config_dram_mr0_cl = 13;
DDRSS.ddr4.config_dram_mr2_cwl = 12;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "5 clocks";

below combinations(cwl=9) can't work, will block in uboot

DDRSS.ddr4.config_dram_mr0_cl = 13;
DDRSS.ddr4.config_dram_mr2_cwl = 9;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "5 clocks";

I will need time to investigate.  There may be some timing associated with the ca_par latency which is requiring the increase in the cas write latency, and it is not getting calculated in the tool correctly.  Let me check

Is CA Parity are requirement for you?  If not, you should be able to disable it.

Regards,

James

hi James

I will need time to investigate.  There may be some timing associated with the ca_par latency which is requiring the increase in the cas write latency, and it is not getting calculated in the tool correctly.  Let me check

    ok, wait your response

Is CA Parity are requirement for you?  If not, you should be able to disable it.

   actually we don't have much experience with DDR , do you recommend to enable CA Parity ?  any other work need to do when enable CA Parity?

in addition, we want to test  the write CRC function, please tell me how to enable the CRC function, I didn't find any related in Sysconfig tool

CA parity would require some software changes to handle the errors correctly.  I don't see too many customers using it.  I would try with is disabled to see if that makes a difference in the CWL setting.

Similarly, write CRC function is typically not used, so enabling that is not available in the Sysconfig tool.  Most customers use the inline ECC feature of the DDR controller to support error correction, if that is what you are ultimately looking for.

Regards,

James

hi James

It looks that the DDR chip IS43QR16256B-083RBLI is not support ECC  ,only support CRC, so we can't use the ECC function , Is it right?  

renew：

I add the property ti,ecc-enable  in the dts file k3-am64-ddr.dtsi  to enable the ECC, system can not boot indeed, will block in uboot

discuss with team， our device may work in very harsh environment, so we may need enable CA Parity and CRC function,   you said "CA parity would require some software changes to handle the errors correctly", so could you provide the sample code for the software change when enable CA parity ?   for the write CRC function, please also help provide the method to enable it  .

we use the linux SDK version 10.01.10.04 

Bert, ECC is a function of the controller, so it will work with your memory.  I suspect you have something wrong in the ECC configuration.  

Software support for CA Parity and CRC is currently not scoped.  If you were to enable these, they would have to be handled with custom code.  Would ECC be enough for your environment if we can get that working?

Regards,

James

Maybe ecc is enough,  we will test .  so for ecc function,  I add the property ti,ecc-enable in the dts file k3-am64-ddr.dtsi to enable it,  Is it right?  any other configurations need to do?

Be sure you compile with the right flags.  More information is here: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/11_01_05_03/exports/docs/linux/Foundational_Components/U-Boot/UG-DDRSS.html

Regards,

James

I am sure add the property ti,ecc-enable in the ddr dtsi file and CONFIG_K3_INLINE_ECC in r5_defconfig file, but still boot failed,  block in uboot.  form the below boot log, you can see ECC is enabled.  we use DDR memory size id 512MB, is it the possible reason ? 

Let me see if i can get help from the software team.

Just to confirm, the boot works if you don't enable ECC?

Regards,

James

confirmed that system boot ok when disable ECC 

Hi Bert,

Do you have SYS_MEM_TOP_HIDE option defined in your U-Boot a53 defconfig? If so, what is its value set to?

yes，below is the value

CONFIG_SYS_MEM_TOP_HIDE=0x2600000

Hi Bert,

When ECC is enabled, the total usable DDR size is 1/9 smaller, which is about 0x3900000. The total DDR size should be 0x1c700000. So there are at least three places in U-Boot which have to adjusted accordingly.

First is the total memory size. In U-Boot devicetree arch/arm/dts/k3-am62x-sk-common.dtsi:

memory@80000000 {
        ...
        reg = <0x00000000 0x80000000 0x00000000 0x80000000>;

You probably already changed its size to 0x20000000. But please now change it 0x1c700000.

The next is the OPTEE load address. It is defined in U-Boot devicetree arch/arm/dts/k3-am62x-sk-common.dtsi:

secure_ddr: optee@9e800000 {
        reg = <0x00 0x9e800000 0x00 0x01800000>; /* for OP-TEE */

Please change its location 0x9e800000 to 0x9af00000.

Finally please add the new optee load address as following in your board a53 defconfig.

CONFIG_K3_OPTEE_LOAD_ADDR=0x9af00000

Hi Bin

sorry for delay response ， still boot failed as you said done, below is the boot log

my dts:

memory@80000000 {
bootph-pre-ram;
device_type = "memory";
/* 512M RAM */
reg = <0x00000000 0x80000000 0x00000000 0x1c700000>;
};

secure_ddr: optee@9e800000 {
reg = <0x00 0x9af00000 0x00 0x01800000>; /* for OP-TEE */
alignment = <0x1000>;
no-map;
};

Hi Bert,

It turns out that the ATF and OPTEE packages have to be recompiled with the new OPTEE load address.

Also currently the DM firmware is located outside of the DDR region once ECC is enabled. It has to be relocated too. I will let you know the details of the change once I figured it out.

BTY,

Bin Liu said:

First is the total memory size. In U-Boot devicetree arch/arm/dts/k3-am62x-sk-common.dtsi:

memory@80000000 {
        ...
        reg = <0x00000000 0x80000000 0x00000000 0x80000000>;

You probably already changed its size to 0x20000000. But please now change it 0x1c700000.

This total memory size change has to be done in arch/arm/dts/k3-am625-sk.dts. It overwrites the memory@8000000 node defined in k3-am62x-sk-common.dtsi.

Hi Bin 

Also currently the DM firmware is located outside of the DDR region once ECC is enabled. It has to be relocated too. I will let you know the details of the change once I figured it out.

 OK, wait your response

This total memory size change has to be done in arch/arm/dts/k3-am625-sk.dts. It overwrites the memory@8000000 node defined in k3-am62x-sk-common.dtsi.

 Actually we use k3-am62-lp-sk.dts, not k3-am625-sk.dts

Hi James

As email mentioned, customer need to send out HW to manufacture line. Do you have any conclusion about their HW design? Is it OK to move forward?

Thanks

Zekun

Hi Bert

I think you can post another thread to discuss CRC and ECC issue with Bin. Better to not mix these two issues.

Thanks

Zekun

Hi Zekun

   Ok

Hi Bin

Bin Liu 

I have create a new thread, let us discuss in it , thanks very much 

e2e.ti.com/.../am623-system-can-t-boot-normally-when-open-ddr-ecc-function

So I think if we can get ECC sorted out, there wouldn't be a need to implement CRC or CA Parity.  Is this correct?

Regards,

James

hi James 

    CRC and CA Parity are not required function now, but I want to know your purpose for the question . Do you mean the HW design should be changed if open CRC and CA Parity ? 

No, i'm just looking to close this thread, and wanted to know if ECC only would meet your needs.

James

hi James 

I will need time to investigate.  There may be some timing associated with the ca_par latency which is requiring the increase in the cas write latency, and it is not getting calculated in the tool correctly.  Let me check

  Do you have any update for your above comment? 

Ok, thanks for the reminder

I just noticed that you are setting the CA parity to "5 clocks".  You should be setting it to "4 clocks", since you are running 1600MTs

Can you try with this setting?

REgards,

James

hi James 

I have already tried following value before,  it can't boot , block in uboot  

DDRSS.ddr4.config_dram_mr0_cl = 13;

DDRSS.ddr4.config_dram_mr2_cwl = 9;
DDRSS.ddr4.config_dram_mr5_ca_par_lat = "4 clocks";

Give me time to investigate more.

James

Hi JJD,

Do you have any update here ?

Regards

Ashwani

Sorry, have not been able to investigate this yet.  Please allow more time

Regards,

James