• State
  • Locked Locked
  • Replies 3 replies
  • Subscribers 98 subscribers
  • Views 481 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

dual TMS320C6745 with ethernet PHY

richard seifert
Prodigy 240 points
Other Parts Discussed in Thread: TMS320C6745, DP83849I, CDCV304

I have an application that will use two TMS320C6745 DSPs.  I want to have a 10/100 ethernet interface to each DSP.  I am looking at using the DP83849 dual Ethernet PHY.  Would it be feasible to have one of the two DSP control the MII serial Management Interface?  The second DSP's Management Interface would be unused.

What is the best way to supply the RMII clock to the DSPs?  Should the CLK2MAC output from the PHY be routed to both DSPs?  Or would it be better to use a low skew clock buffer and send a copy of the 50MHz clock source to each DSP and the PHY and disable the CLK2MAC output?

  • 0
    TI__Mastermind 27585 points

    Yes you can just use one of the DSPs to handle the PHY MII interface.

    How to hook up the RMII clock to the DSPs would depend on the drive strength of the PHY. It should come with IBIS models which you could use to simulate your board to determine if the signals will still meet the DSP datasheet timings. Most likely it would be ok to drive both simultaneously, but you would at least want to length match the trace from PHY to each DSP.

    Jeff

  • 0 in reply to jc-ti
    Prodigy 240 points

    Let me be more specific about my confusion with the RMII clock.  I am using AN-1405 as my guide in connecting the RMII interface between the DP83849I and the TMS320C6745.  The application note is for the DP83848, but I was assuming that it would also apply to the DP83849.  In section 3.1, it states that the 25MHz_OUT signal will be a 50MHZ clock in RMII mode and SHOULD NOT BE USED AS THE TIMING REFERENCE FOR RMII CONTROL AND DATA SIGNALS.  Comparing the DP83848 and DP83849 datasheets, 25MHZ_OUT seems analagous to the CLK2MAC signal.  My specific question is: Should CLK2MAC be used as the clock input to the RMII_MHZ_50_CLK input of the TMS320C6745?

    The alternate approcach would be use the signal that drives X1 as the clock input to the RMII_MHZ_50_CLK input of the TMS320C6745.  I could use a low skew clock buffer such as the CDCV304 to generate 3 clocks, one for the PHY and one for each of the DSPs.

  • 0 in reply to richard seifert
    TI__Mastermind 27585 points

    If the PHY specifically states that its output shouldn't be used as the timing reference, then I would suggest using an external clock to source all 3 as you stated.

    Jeff