AM62P-Q1: RGMII output clock change to 125MHz failed

Hi Changxing, 

1. What operating system are you using?

2. Are you using the Linux SDK? If so, what SDK version are you using?

3. Are you working with a custom board? If so, did you change any hardware components related to the clocking system from the AM62P TI EVM?

-Daolin

Os: LInux 

Linux SDK version 10.0

Our own board, for EVM it is OK.

Our phy is marvell 88q5152.

RXC from Phy is 125 MHz, but Soc out put is 25MHz.

Hi Changxing Du, 

Thanks for answering my questions.

Let me loop in a hardware expert on this topic to first check if there potentially could be something from the hardware side that is missing.

Please kindly ping this thread if you don't hear a response by Wednesday.

-Daolin

Hi All, 

I am not sure if there is any hardware information that i can check.

FYI, the SK implements RGMII.

Are you connecting EPHY and is the EPHY at 1000M?

Regards,

Sreenivasa

Hi Changxing Du, 

Changxing Du said:

We changed the MAC control register bit 7 to gigabit mode, the current mac controll register is 0xa1, but the out put clock is still 25MHz, is there any thing we should check ?

May I ask specifically why this register was manually modified? Usually, a link has to be established before the clock starts up. If the link speed is set to 1000Mbps, then by default the clock speed should be at 125MHz without any manual changes needed to be made. This is how the AM62P EVM works as well when running on Linux OS. 

It seems that you are possibly trying to bypass the link establishment process? Am I correct with this understanding? If so, why are you trying to bypass it?

-Daolin

Hello 

We use the Marvel 88q5152, we do not change is mannualy, we just change the phy->link to up and phy-speed to 1000, the uboot then try to change the mac control register to 0xA1.

Additionally could help clarity how the GMII_RFT_CLK is selected, it is by any register or automatically once the mac control register is set?

Hi Changxing,

if possible, pls involve Marvel technical support for your case as well.

BR,

Biao 

Hi Changxing Du,

Thanks for clarifying that you are using a Marvel Ethernet PHY, as Biao Li mentioned, for checking the PHY side, please check with Marvel to ensure your PHY is also correctly configured.

Changxing Du said:

the uboot then try to change the mac control register to 0xA1.

What I meant by "manual" is exactly this action of changing the registers. This typically is not a necessary step as I explained in my previous message. The below suggestions are assuming you do not make changes to the registers.

What is your network hardware setup? (i.e. what link partner is connected to your custom board? Is it a direct connection or is there a switch involved?)

Can you share what is the result of "ethtool <eth interface name you are testing>"? We want to see what the linked speed is. 

Can you share what is your device tree? We want to see if you selected the correct interface mode and speed.

Changxing Du said:

Additionally could help clarity how the GMII_RFT_CLK is selected, it is by any register or automatically once the mac control register is set?

My understanding is that the Linux drivers should already handle clock configuration as well as all necessary MAC register configurations to bring up your Ethernet interface and that the only changes that are necessary on your end is ensuring your device tree is correctly configured and you didn't unknowingly connect to a lower link speed link partner (assuming there are no issues on your Marvel PHY configuration and custom hardware). 

-Daolin

Hello Daolin

Thanks for your clarification.

THe issue has been fixed.

Our Link speed is 1000 for the u-boot .

The MAC automatcially detect the speed from phy. But the latency is not enabled at PHY side which can lead to fail to detect the speed.

B.R.

Changxing Du