Other Parts Discussed in Thread: DP83869
Tool/software:
Hi,
I am working on enabling CPSW9G on the J784S4 SoC with the following hardware setup:
- DP83869 SGMII-to-RGMII PHY (Address: 0x3)
- Connected over SGMII5 via SERDES2_LANE0
- SoC side: `SGMII5_RX0_P/N`, `TX0_P/N` are routed to `SERDES2_RX0_P/N` and `TX0_P/N` respectively
- I have updated the device tree as follows:
-
#include <dt-bindings/net/ti-dp83869.h> // for DP83869 macros
&main_cpsw0 {
status = "okay";
phys = <&serdes2_qsgmii_link>;
phy-names = "serdes";
};&main_cpsw0_port1 {
status = "okay";
phy-mode = "qsgmii";
phy-handle = <&main_phy3>;
phys = <&cpsw0_phy_gmii_sel 5>, <&serdes2_qsgmii_link>;
phy-names = "mac", "serdes";
};&main_cpsw0_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_cpsw9x1_pins_default>;
pinctrl-1 = <&main_pmx_gpio_vddshv20_pins_default>;main_phy3: ethernet-phy@3 {
reg = <3>;
ti,op-mode = <DP83869_RGMII_SGMII_BRIDGE>;
};
};&serdes_ln_ctrl {
idle-states = <
...
J784S4_SERDES2_LANE0_QSGMII_LANE5
...
>;
};&serdes_wiz2 {
status = "okay";
};&serdes2 {
status = "okay";
#address-cells = <1>;
#size-cells = <0>;serdes2_qsgmii_link: phy@0 {
reg = <0>;
cdns,num-lanes = <1>;
cdns,phy-type = <PHY_TYPE_QSGMII>;
#phy-cells = <0>;
resets = <&serdes_wiz2 3>;
};
}; - Query:
- Could you please confirm if this configuration is sufficient and correct to enable SGMII5 on SERDES2_LANE0 using CPSW9G and DP83869 on J784S4?
- Is using `cpsw0_phy_gmii_sel` correct for `main_cpsw0_port1`?
- Is `phy-mode = "qsgmii"` mandatory, even though only one SGMII link is used (SGMII5)?
- Is the usage of `J784S4_SERDES2_LANE0_QSGMII_LANE5` macro appropriate in `serdes_ln_ctrl`?
Thanks in advance!
Best Regards,
Apuroop
