TDA4VM: Mailbox interrupt doesn't trigger after CPU reset using IPC baremetal + CSL

Tool/software:

Hello,

I'm working on a baremetal project for the Cortex-R5 (Main domain).

I'm using the IPC driver only, specifically the Mailbox support from:

ti/drv/ipc/src/mailbox/csl_mailbox.h

I'm not using MCAL or AUTOSAR in this setup.

To configure the interrupts, I'm using the CSL (Chip Support Library), both for the VIM (Vector Interrupt Manager) and the Interrupt Router (INTRTR). I have verified that the interrupt routing is working (when I send a message locally from the receiver core itself, the interrupt triggers successfully).

What's working:

• The mailbox interrupt fires correctly when the message is sent by the same R5 core that also receives it (loopback test).

• The VIM interrupt setup and NAVSS INTR Router configuration are handled entirely with CSL and confirmed to work.

The issue:

When I reset the CPU (via CPU Reset or Restart in CCS), or when I run the sender core (R5FSS1-0) to send a message to the receiver core (R5FSS0-0), the interrupt does not trigger.

More specifically:

• No interrupt is triggered when the sender sends a message.

• I'm not using  MailboxReset() (as it’s only available in the MCAL), and the IPC baremetal mailbox driver does not seem to provide a similar API.

• The same code works fine on first boot, but fails after a CPU-only reset.

My questions:

1. Since I'm not using MCAL, what’s the correct initialization or reset sequence I need to perform for the Mailbox peripheral after a CPU reset?

2. Do I need to manually clear any registers to re-enable interrupt functionality?

3. Is this behavior expected due to how the mailbox state is preserved between resets?

4. Is there any clean minimal setup or workaround to reliably reinitialize the Mailbox for interrupt use without using the full MCAL layer?

My codes:

Sender:

#include <stdint.h>
#include <ti/csl/soc.h>
#include <stdio.h>
#include <ti/drv/ipc/src/mailbox/csl_mailbox.h>

#define MAILBOX0_BASE_ADDR     (CSL_NAVSS0_MAILBOX_REGS0_BASE)
#define QUEUE_ID               MAILBOX_QUEUE_0
#define USER_ID                1U
#define MENSAGEM               (0xDEADBEEF)

int main(void)
{
    uint32_t status;
    while (1)
    {
        status = Mailbox_sendMessage(MAILBOX0_BASE_ADDR, QUEUE_ID, MENSAGEM);
    }
    return 0;
}

#include <stdint.h>
#include <stdio.h>
#include <ti/csl/soc.h>
#include <mwfal/mwfintc/interrupt_config.h>
#include <ti/drv/ipc/src/mailbox/csl_mailbox.h>

#define MAILBOX0_BASE_ADDR     (CSL_NAVSS0_MAILBOX_REGS0_BASE)
#define QUEUE_ID               MAILBOX_QUEUE_0
#define USER_ID                0U
#define VIM_CHANNEL_MAILBOX    224

void mailbox_isr(void *arg)
{
    uint32_t mensagem = 0;
    if (Mailbox_getRawNewMsgStatus(MAILBOX0_BASE_ADDR, USER_ID, QUEUE_ID))
    {
        Mailbox_getMessage(MAILBOX0_BASE_ADDR, QUEUE_ID, &mensagem);
        printf("Received via IRQ: %u (0x%08X)\n", mensagem, mensagem);
        Mailbox_clrNewMsgStatus(MAILBOX0_BASE_ADDR, USER_ID, QUEUE_ID);
        HW_WR_REG32(MAILBOX0_BASE_ADDR + CSL_MAILBOX_IRQ_EOI, USER_ID);
    }
}

void init_interrupts(void)
{
    Mailbox_disableNewMsgInt(MAILBOX0_BASE_ADDR, USER_ID, QUEUE_ID);
    Mailbox_enableNewMsgInt(MAILBOX0_BASE_ADDR, USER_ID, QUEUE_ID);
    Mailbox_clrNewMsgStatus(MAILBOX0_BASE_ADDR, USER_ID, QUEUE_ID);

    InterruptConfig mboxIntCfg = {
        .channel = VIM_CHANNEL_MAILBOX,
        .priority = 0,
        .mapType = INTR_MAP_IRQ,
        .triggerType = INTR_TYPE_LEVEL,
        .callback = mailbox_isr,
        .callbackArg = NULL
    };
    interrupt_init(&mboxIntCfg);
}

int main(void)
{
    init_interrupts();

    uint32_t msg = 0;
    Mailbox_getMessage(MAILBOX0_BASE_ADDR, QUEUE_ID, &msg);

    while (1)
    {
        // waiting for interrupt
    }
    return 0;
}

#include <stdint.h>
#include <ti/csl/csl_intr_router.h>
#include <ti/csl/soc.h>

#define R5FSS0_0_OUTL_INDEX   192U
#define R5FSS1_0_OUTL_INDEX   256U
#define MAILBOX0_R5FSS0_0_IN  436U
#define MAILBOX0_R5FSS1_0_IN  437U

void configure_navss_intr_router(void)
{
    CSL_IntrRouterCfg NAVSS0 = {
        .pIntrRouterRegs = (CSL_intr_router_cfgRegs *)CSL_NAVSS0_INTR0_INTR_ROUTER_CFG_BASE,
        .pIntdRegs       = NULL,
        .numInputIntrs   = 447,
        .numOutputIntrs  = 407
    };

    CSL_intrRouterCfgMux(&NAVSS0, MAILBOX0_R5FSS0_0_IN, R5FSS0_0_OUTL_INDEX);
    CSL_intrRouterCfgMux(&NAVSS0, MAILBOX0_R5FSS1_0_IN, R5FSS1_0_OUTL_INDEX);
}

VIM Interrupt Config (CSL-based):

// interrupt_config.c
#include "interrupt_config.h"

void interrupt_init(const InterruptConfig *config)
{
    Intc_Init();
    Intc_IntEnable(config->channel);
    Intc_IntSetSrcType(config->channel, (uint32_t)config->triggerType);
    Intc_IntPrioritySet(config->channel, config->priority, (uint32_t)config->mapType);
    Intc_IntRegister(config->channel, config->callback, config->callbackArg);
    Intc_SystemEnable();
}

Any insights into how to fully reinitialize the Mailbox peripheral in this setup would be greatly appreciated.

Regards,

Heverton