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Tool/software:
Hello,
We are using the tidl model import tool, and we found that when the convolutional layer is set to 16-bit, the board-end demo will crash when running to this convolutional layer.
We tested and found that only the convolutional layer with a gridsample layer before it would cause this issue.
All the data is in the compressed package.
Regards,
hongyao
Hi,
I test it on 11.0.8.0 tidl with edgeai tidl tools. I cannot reproduce this issue.
My import log:
(tidl_11_00) ht@ht:~/edgeai/edgeai-tidl-tools/examples/osrt_python/ort$ python3 onnxrt_ep.py -c -m gridsample16bit
Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']
Running 1 Models - ['gridsample16bit']
Running_Model : gridsample16bit
Running shape inference on model ../../../models/public/girdsample16bit.onnx
tidl_tools_path = /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools
artifacts_folder = ../../../model-artifacts//gridsample16bit/artifacts
tidl_tensor_bits = 16
debug_level = 1
num_tidl_subgraphs = 16
num_tidl_subgraph_max_node = 0
enable_rt_multi_subgraph_support = 0
tidl_denylist =
tidl_denylist_layer_name =
tidl_denylist_layer_type =
tidl_allowlist_layer_name =
model_type =
tidl_calibration_accuracy_level = 7
tidl_calibration_options:num_frames_calibration = 2
tidl_calibration_options:bias_calibration_iterations = 5
mixed_precision_factor = -1.000000
model_group_id = 0
power_of_2_quantization = 2
ONNX QDQ Enabled = 0
enable_high_resolution_optimization = 0
pre_batchnorm_fold = 1
add_data_convert_ops = 3
output_feature_16bit_names_list =
m_params_16bit_names_list =
m_single_core_layers_names_list =
m_spatial_split_layers_names_list =
m_channel_split_layers_names_list =
Inference mode = 0
Number of cores = 1
reserved_compile_constraints_flag = 83886080
partial_init_during_compile = 0
packetize_mode = 0
enable_tfr_optimization = 0
ti_internal_reserved_1 =
========================= [Model Compilation Started] =========================
Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning
============================== [Version Summary] ==============================
-------------------------------------------------------------------------------
| TIDL Tools Version | 11_00_08_00 |
-------------------------------------------------------------------------------
| C7x Firmware Version | 11_00_08_00 |
-------------------------------------------------------------------------------
| Runtime Version | 1.15.0 |
-------------------------------------------------------------------------------
| Model Opset Version | 16 |
-------------------------------------------------------------------------------
============================== [Parsing Started] ==============================
[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - GridSample, Node name - /bev_encoder/GridSample_5 -- [tidl_onnxRtImport_core.cpp, 626]
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Reshape, Node name - /bev_encoder/Reshape_18 -- [tidl_onnxRtImport_core.cpp, 626]
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Conv, Node name - /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv -- [tidl_onnxRtImport_core.cpp, 626]
------------------------- Subgraph Information Summary -------------------------
-------------------------------------------------------------------------------
| Core | No. of Nodes | Number of Subgraphs |
-------------------------------------------------------------------------------
| C7x | 3 | 1 |
| CPU | 0 | x |
-------------------------------------------------------------------------------
Running Runtimes GraphViz - /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//gridsample16bit/artifacts/allowedNode.txt ../../../model-artifacts//gridsample16bit/artifacts/tempDir/graphvizInfo.txt ../../../model-artifacts//gridsample16bit/artifacts/tempDir/runtimes_visualization.svg
============================= [Parsing Completed] =============================
TIDL_createStateImportFunc Started:
Compute on node : TIDLExecutionProvider_TIDL_0_0
0, GridSample, 2, 1, /bev_encoder/Reshape_15_output_0, /bev_encoder/GridSample_5_output_0
1, Reshape, 2, 1, /bev_encoder/GridSample_5_output_0, /bev_encoder/Reshape_18_output_0
2, Conv, 3, 1, /bev_encoder/Reshape_18_output_0, /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
Input tensor name - /bev_encoder/Reshape_15_output_0
Input tensor name - /bev_encoder/Unsqueeze_5_output_0
Output tensor name - /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
In TIDL_onnxRtImportInit subgraph_name=subgraph_0
Layer 0, subgraph id subgraph_0, name=/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
Layer 1, subgraph id subgraph_0, name=/bev_encoder/Reshape_15_output_0
Layer 2, subgraph id subgraph_0, name=/bev_encoder/Unsqueeze_5_output_0
==================== [Optimization for subgraph_0 Started] ====================
In TIDL_runtimesOptimizeNet: LayerIndex = 6, dataIndex = 5
----------------------------- Optimization Summary -----------------------------
--------------------------------------------------------------------------------
| Layer | Nodes before optimization | Nodes after optimization |
--------------------------------------------------------------------------------
| TIDL_TransposeLayer | 0 | 2 |
| TIDL_ConvolutionLayer | 1 | 1 |
| TIDL_GridSampleLayer | 1 | 1 |
--------------------------------------------------------------------------------
Total nodes in subgraph: 11
=================== [Optimization for subgraph_0 Completed] ===================
In TIDL_runtimesPostProcessNet
************ in TIDL_subgraphRtCreate ************
The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
0.3s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
************ TIDL_subgraphRtCreate done ************
============= [Quantization & Calibration for subgraph_0 Started] =============
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles,
2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Sum of Layer Cycles 0
Sub Graph Stats 45.000000 1947428.000000 4721.000000
******* TIDL_subgraphRtInvoke done ********
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles,
2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Sum of Layer Cycles 0
Sub Graph Stats 31.000000 1927860.000000 593.000000
******* TIDL_subgraphRtInvoke done ********
In TIDL_runtimesPostProcessNet
-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [1 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [2 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [3 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [4 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [5 / 5]: ------------------
[=============================================================================] 100 %
==================== [Quantization & Calibration Completed] ====================
========================== [Memory Planning Started] ==========================
------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation
========================= [Memory Planning Completed] =========================
Rerunning network compiler...
========================== [Memory Planning Started] ==========================
------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation
========================= [Memory Planning Completed] =========================
======================== Subgraph Compiled Successfully ========================
Completed_Model : 1, Name : gridsample16bit , Total time : 17590.16, Offload Time : 1937.64 , DDR RW MBs : 0, Output Image File : py_out_gridsample16bit_ADE_val_00001801.jpg, Output Bin File : py_out_gridsample16bit_ADE_val_00001801.bin
************ in TIDL_subgraphRtDelete ************
MEM: Deinit ... !!!
MEM: Alloc's: 27 alloc's of 413633405 bytes
MEM: Free's : 27 free's of 413633405 bytes
MEM: Open's : 0 allocs of 0 bytes
MEM: Deinit ... Done !!!
(tidl_11_00) ht@ht:~/edgeai/edgeai-tidl-tools/examples/osrt_python/ort$
My infer log on evm:
root@am69-sk:/opt/edgeai/edgeai-tidl-tools/examples/osrt_python/ort# python3 onnxrt_ep.py -m gridsample16bit
Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']
Running 1 Models - ['gridsample16bit']
Running_Model : gridsample16bit
libtidl_onnxrt_EP loaded 0x12eb4cf0
artifacts_folder = ../../../model-artifacts//gridsample16bit/artifacts
debug_level = 1
target_priority = 0
max_pre_empt_delay = 340282346638528859811704183484516925440.000000
Final number of subgraphs created are : 1, - Offloaded Nodes - 3, Total Nodes - 3
In TIDL_createStateInfer
Compute on node : TIDLExecutionProvider_TIDL_0_0
************ in TIDL_subgraphRtCreate ************
APP: Init ... !!!
12750.521550 s: MEM: Init ... !!!
12750.521599 s: MEM: Initialized DMA HEAP (fd=5) !!!
12750.521728 s: MEM: Init ... Done !!!
12750.521749 s: IPC: Init ... !!!
12750.556949 s: IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
12750.564717 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
12750.564827 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
12750.564838 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
12750.564846 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
12750.565379 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0
12750.565534 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1
12750.565632 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2
12750.565720 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3
12750.565732 s: VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
12750.565744 s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
************ TIDL_subgraphRtCreate done ************
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoef,
2, 36344, 6212, 8415, 8701, 9115, 0, 0, ,
4, 18309, 3149, 4444, 5816, 1753, 0, 0, ,
3, 43103, 10774, 11934, 7181, 18079, 0, 0, ,
5, 1985476, 1962581, 1964107, 9198, 4192, 0, 0, ,
6, 331921, 155041, 312430, 6434, 7035, 0, 0, ,
7, 4275, 0, 0, 0, 0, 0, 0, ,
8, 6714680, 5855559, 6675538, 20993, 12267, 0, 0, ,
9, 875465, 289783, 857259, 8603, 4156, 0, 0, ,
Sum of Layer Cycles 10009573
Sub Graph Stats 259.000000 10954.000000 10327.000000
******* TIDL_subgraphRtInvoke done ********
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoef,
2, 40585, 6178, 8273, 12635, 9053, 0, 0, ,
4, 17893, 2881, 4342, 5717, 1693, 0, 0, ,
3, 42669, 10660, 11725, 7506, 17925, 0, 0, ,
5, 1986091, 1962286, 1964700, 9451, 4297, 0, 0, ,
6, 332683, 154987, 312733, 7378, 7346, 0, 0, ,
7, 4631, 0, 0, 0, 0, 0, 0, ,
8, 6710834, 5852129, 6671814, 20965, 12164, 0, 0, ,
9, 871298, 290952, 852805, 8490, 4012, 0, 0, ,
Sum of Layer Cycles 10006684
Sub Graph Stats 234.000000 10847.000000 340636.000000
******* TIDL_subgraphRtInvoke done ********
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoef,
2, 40639, 7281, 9292, 12618, 8986, 0, 0, ,
4, 18379, 2933, 4520, 6048, 1681, 0, 0, ,
3, 42273, 10641, 11634, 7412, 17921, 0, 0, ,
5, 1985382, 1962084, 1963269, 10111, 4190, 0, 0, ,
6, 331540, 154614, 311655, 7090, 7037, 0, 0, ,
7, 4287, 0, 0, 0, 0, 0, 0, ,
8, 6708951, 5851043, 6669997, 20835, 12257, 0, 0, ,
9, 868866, 290377, 851007, 7790, 4057, 0, 0, ,
Sum of Layer Cycles 10000317
Sub Graph Stats 236.000000 10841.000000 6765.000000
******* TIDL_subgraphRtInvoke done ********
Completed_Model : 1, Name : gridsample16bit , Total time : 11.19, Offload Time : 10.88 n
************ in TIDL_subgraphRtDelete ************
APP: Deinit ... !!!
REMOTE_SERVICE: Deinit ... !!!
REMOTE_SERVICE: Deinit ... Done !!!
12751.042321 s: IPC: Deinit ... !!!
12751.043273 s: IPC: DeInit ... Done !!!
12751.377748 s: MEM: Deinit ... !!!
12751.377767 s: DDR_SHARED_MEM: Alloc's: 8 alloc's of 20016464 bytes
12751.377775 s: DDR_SHARED_MEM: Free's : 8 free's of 20016464 bytes
12751.377782 s: DDR_SHARED_MEM: Open's : 0 allocs of 0 bytes
12751.377797 s: MEM: Deinit ... Done !!!
APP: Deinit ... Done !!!
root@am69-sk:/opt/edgeai/edgeai-tidl-tools/examples/osrt_python/ort#
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Offline | ttyUSB2
But I will try rtos tools to see if it can be reproduced on rtos tool.
Regards,
Adam
Hi
I am also able to run it with rtos tool:
On evm:
root@j784s4-evm:/opt/0711_simple_demo2# ./TI_DEVICE_armv8_test_dl_algo_host_rt.out s:tidl_infer.txt
Processing config file #0 : tidl_infer.txt
Input : dataId=0, name=/bev_encoder/Reshape_15_output_0, elementType 6, scale=1.000000, zero point=0, layout=0
Input : dataId=1, name=/bev_encoder/Unsqueeze_5_output_0, elementType 6, scale=1.000000, zero point=0, layout=0
Ouput : dataId=9, name=/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0, elementType 6, scale=1.000000, zero point=0,
1923980, 1.835 0xffff4b1db010
worstCaseDelay for Pre-emption is 10.7719469
Network File Read done
APP: Init ... !!!
103.762041 s: MEM: Init ... !!!
103.762086 s: MEM: Initialized DMA HEAP (fd=5) !!!
103.762240 s: MEM: Init ... Done !!!
103.762256 s: IPC: Init ... !!!
103.797242 s: IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
103.806029 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
103.807829 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
103.807847 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
103.807855 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
103.809870 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0
103.809990 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1
103.810071 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2
103.810187 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3
103.810198 s: VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
103.810208 s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[C7x_1 ] 103.826472 s: TIDL_initDebugTraceParams Done
[C7x_1 ] 103.826583 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 103.826612 s: ===================================================
[C7x_1 ] 103.826648 s: Link Id 1073741888, Number of TR required = 1
[C7x_1 ] 103.826676 s: ===================================================
[C7x_1 ] 103.826709 s: Link Id 536870960, Number of TR required = 3
[C7x_1 ] 103.826737 s: ===================================================
[C7x_1 ] 103.826770 s: Link Id 2684354656, Number of TR required = 1
[C7x_1 ] 103.826798 s: ===================================================
[C7x_1 ] 103.826827 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 103.826854 s: ===================================================
[C7x_1 ] 103.826891 s: Link Id 3758096512, Number of TR required = 3
[C7x_1 ] 103.826919 s: ===================================================
[C7x_1 ] 103.826948 s: Link Id 3808428160, Number of TR required = 1
[C7x_1 ] 103.826976 s: ===================================================
[C7x_1 ] 103.827005 s: Link Id 3825205376, Number of TR required = 1
[C7x_1 ] 103.827032 s: ===================================================
[C7x_1 ] 103.827061 s: Link Id 3841982592, Number of TR required = 1
[C7x_1 ] 103.827088 s: ===================================================
[C7x_1 ] 103.827402 s: Link Id 4294967440, Number of TR required = 1
[C7x_1 ] 103.827430 s: ===================================================
[C7x_1 ] 103.827461 s: Link Id 4378853520, Number of TR required = 2
[C7x_1 ] 103.827489 s: ===================================================
[C7x_1 ] 103.827540 s: PREEMPTION: Requesting memory of size 3014656 for targetPriority = 256
[C7x_1 ] 103.827560 s:
[C7x_1 ] 103.827579 s: --------------------------------------------
[C7x_1 ] 103.827604 s: TIDL Memory size requiement (record wise):
[C7x_1 ] 103.827644 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
[C7x_1 ] 103.827690 s: 0 , DDR Non-cacheable , Persistent , 128, 19.67 , 0x00000000
[C7x_1 ] 103.827732 s: 1 , DDR Cacheable , Persistent , 128, 0.66 , 0x00000000
[C7x_1 ] 103.827773 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000
[C7x_1 ] 103.827815 s: 3 , L2 , Scratch , 128, 448.00 , 0x00000000
[C7x_1 ] 103.827856 s: 4 , L3/MSMC , Scratch , 128, 2944.00 , 0x00000000
[C7x_1 ] 103.827897 s: 5 , DDR Cacheable , Persistent , 128, 316.81 , 0x00000000
[C7x_1 ] 103.827938 s: 6 , DDR Non-cacheable , Scratch , 128, 1.25 , 0x00000000
[C7x_1 ] 103.827979 s: 7 , DDR Non-cacheable , Persistent , 128, 25280.25, 0x00000000
[C7x_1 ] 103.828019 s: 8 , DDR Non-cacheable , Scratch , 128, 0.13 , 0x00000000
[C7x_1 ] 103.828060 s: 9 , DDR Non-cacheable , Scratch , 128, 3.13 , 0x00000000
[C7x_1 ] 103.828101 s: 10 , DDR Cacheable , Persistent , 128, 321.88 , 0x00000000
[C7x_1 ] 103.828142 s: 11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x00000000
[C7x_1 ] 103.828183 s: 12 , DDR Non-cacheable , Persistent , 128, 2944.00 , 0x00000000
[C7x_1 ] 103.828224 s: 13 , DDR Cacheable , Persistent , 128, 1302.51 , 0x00000000
[C7x_1 ] 103.828264 s: 14 , DDR Non-cacheable , Persistent , 128, 0.00 , 0x00000000
RT-Profile: TIDLRT_init_profiling
[C7x_1 ] 103.828305 s: 15 , DDR Cacheable , Persistent , 128, 578.25 , 0x00000000
tidlrt_create : 86362155 ns,
tidl_rt_ovx_Init : 52598080 ns,
vxCreateContext : 3667680 ns,
[C7x_1 ] 103.828334 s: --------------------------------------------
init_tidl_tiovx : 3744800 ns,
create_graph_tidl_tiovx : 2662655 ns,
verify_graph_tidl_tiovx : 23276235 ns,
[C7x_1 ] 103.828359 s: Total memory size requirement (space wise):
tivxTIDLLoadKernels : 14890 ns,
mapConfig : 944320 ns,
tivxAddKernelTIDL : 104760 ns,
[C7x_1 ] 103.828380 s: Mem Space , Size(KBytes)
mapNetwork : 2178755 ns,
setCreateParams : 205765 ns,
[C7x_1 ] 103.828397 s: L1D , 16.00
setArgs : 294620 ns,
vxCreateUserDataObject : 2707250 ns,
[C7x_1 ] 103.828414 s: L2 , 448.00
vxMapUserDataObject : 1415540 ns,
memcopy_network_buffer : 728850 ns,
[C7x_1 ] 103.828432 s: L3/MSMC , 2944.00
vxUnmapUserDataObject : 3275 ns,
[C7x_1 ] 103.828450 s: DDR Cacheable, 6616.36
# NETWORK_INIT_TIME = 407.96 (in ms, c7x @1GHz)
[C7x_1 ] 103.828470 s: DDR Non-cacheable, 28248.42
[C7x_1 ] 103.828493 s: --------------------------------------------
[C7x_1 ] 103.828529 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
[C7x_1 ] 103.828568 s: To get the actual TIDL memory requirement make sure to run on EVM with
[C7x_1 ] 103.828592 s: debugTraceLevel = 2
[C7x_1 ] 103.828601 s:
[C7x_1 ] 103.828621 s: --------------------------------------------
[C7x_1 ] 103.828695 s: TIDL init call from ivision API
[C7x_1 ] 103.828710 s:
Freeing memory for user provided Net
[C7x_1 ] 103.828728 s: --------------------------------------------
[C7x_1 ] 103.828753 s: TIDL Memory size requiement (record wise):
[C7x_1 ] 103.828792 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
[C7x_1 ] 103.828835 s: 0 , DDR Non-cacheable , Persistent , 128, 19.67 , 0x00000000
[C7x_1 ] 103.828877 s: 1 , DDR Cacheable , Persistent , 128, 0.66 , 0x0806c400
[C7x_1 ] 103.828919 s: 2 , L1D , Scratch , 128, 16.00 , 0x64e00000
[C7x_1 ] 103.828960 s: 3 , L2 , Scratch , 128, 448.00 , 0x64800000
[C7x_1 ] 103.829001 s: 4 , L3/MSMC , Scratch , 128, 2944.00 , 0x68000000
[C7x_1 ] 103.829042 s: 5 , DDR Cacheable , Persistent , 128, 316.81 , 0x0806c800
[C7x_1 ] 103.829083 s: 6 , DDR Non-cacheable , Scratch , 128, 1.25 , 0x10000000
[C7x_1 ] 103.829124 s: 7 , DDR Non-cacheable , Persistent , 128, 25280.25, 0x00005000
[C7x_1 ] 103.829172 s: 8 , DDR Non-cacheable , Scratch , 128, 0.13 , 0x10000800
[C7x_1 ] 103.829213 s: 9 , DDR Non-cacheable , Scratch , 128, 3.13 , 0x10000c00
[C7x_1 ] 103.829255 s: 10 , DDR Cacheable , Persistent , 128, 321.88 , 0x080bbd00
[C7x_1 ] 103.829296 s: 11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x18000000
[C7x_1 ] 103.829337 s: 12 , DDR Non-cacheable , Persistent , 128, 2944.00 , 0x018b5400
[C7x_1 ] 103.829378 s: 13 , DDR Cacheable , Persistent , 128, 1302.51 , 0x0810c600
[C7x_1 ] 103.829418 s: 14 , DDR Non-cacheable , Persistent , 128, 0.00 , 0x01b95400
[C7x_1 ] 103.829460 s: 15 , DDR Cacheable , Persistent , 128, 578.25 , 0x08252200
Instance created for tidl_infer.txt
[C7x_1 ] 103.829488 s: --------------------------------------------
[C7x_1 ] 103.829513 s: Total memory size requirement (space wise):
[C7x_1 ] 103.829533 s: Mem Space , Size(KBytes)
[C7x_1 ] 103.829550 s: L1D , 16.00
[C7x_1 ] 103.829567 s: L2 , 448.00
[C7x_1 ] 103.829584 s: L3/MSMC , 2944.00
[C7x_1 ] 103.829602 s: DDR Cacheable, 6616.36
[C7x_1 ] 103.829621 s: DDR Non-cacheable, 28248.42
[C7x_1 ] 103.829645 s: --------------------------------------------
Processing Cnt : 0, InstCnt : 0 subgraph_0_tidl_net.bin!
[C7x_1 ] 103.829680 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
[C7x_1 ] 103.829719 s: To get the actual TIDL memory requirement make sure to run on EVM with
[C7x_1 ] 103.829743 s: debugTraceLevel = 2
[C7x_1 ] 103.829753 s:
[C7x_1 ] 103.829773 s: --------------------------------------------
[C7x_1 ] 103.832550 s: Alg Init for Layer # - 2
[C7x_1 ] 103.832599 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 103.832627 s: ===================================================
[C7x_1 ] 103.832657 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 103.832685 s: ===================================================
[C7x_1 ] 103.832715 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 103.832743 s: ===================================================
[C7x_1 ] 103.832762 s: Link Index 32
[C7x_1 ] 103.832786 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 103.832818 s: Link->src-> icnt (dim); 432 64 (432) 1 (432) 1 (27648)
[C7x_1 ] 103.832852 s: Link->sink-> icnt (dim); 432 64 (432) 1 (13824) 1 (0)
[C7x_1 ] 103.832872 s: srcMemPtr: 0
[C7x_1 ] 103.832888 s: dstMemPtr: 1686110208
[C7x_1 ] 103.832948 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 103.832975 s: ===================================================
[C7x_1 ] 103.833001 s: Alg Init for Layer # - 4
[C7x_1 ] 103.833038 s: Link Id 1073741888, Number of TR required = 1
[C7x_1 ] 103.833066 s: ===================================================
[C7x_1 ] 103.833097 s: Link Id 1073741888, Number of TR required = 1
[C7x_1 ] 103.833125 s: ===================================================
[C7x_1 ] 103.833157 s: Link Id 1073741888, Number of TR required = 1
[C7x_1 ] 103.833184 s: ===================================================
[C7x_1 ] 103.833205 s: Link Index 1073741888
[C7x_1 ] 103.833229 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 103.833258 s: Link->src-> icnt (dim); 27648 1 (0) 1 (0) 1 (0)
[C7x_1 ] 103.833290 s: Link->sink-> icnt (dim); 27648 1 (27648) 1 (0) 1 (0)
[C7x_1 ] 103.833311 s: srcMemPtr: 1744885760
[C7x_1 ] 103.833328 s: dstMemPtr: 1686110208
[C7x_1 ] 103.833383 s: Link Id 1073741888, Number of TR required = 1
[C7x_1 ] 103.833412 s: ===================================================
[C7x_1 ] 103.833437 s: Alg Init for Layer # - 3
[C7x_1 ] 103.833473 s: Link Id 536870960, Number of TR required = 3
[C7x_1 ] 103.833501 s: ===================================================
[C7x_1 ] 103.833531 s: Link Id 536870960, Number of TR required = 3
[C7x_1 ] 103.833559 s: ===================================================
[C7x_1 ] 103.833589 s: Link Id 536870960, Number of TR required = 3
[C7x_1 ] 103.833617 s: ===================================================
[C7x_1 ] 103.833638 s: Link Index 536870960
[C7x_1 ] 103.833660 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 103.833693 s: Link->src-> icnt (dim); 32768 2 (32768) 1 (65536) 1 (65536)
[C7x_1 ] 103.833728 s: Link->sink-> icnt (dim); 32768 2 (32768) 1 (32768) 1 (0)
Warning :: File read for binary data load is not suffcient in size to fill the input tensor, Filling it with zero
[C7x_1 ] 103.833747 s: srcMemPtr: 0
[C7x_1 ] 103.833764 s: dstMemPtr: 1686110208
[C7x_1 ] 103.833818 s: Link Id 536870960, Number of TR required = 3
[C7x_1 ] 103.833846 s: ===================================================
[C7x_1 ] 103.833871 s: Alg Init for Layer # - 5
[C7x_1 ] 103.833912 s: Link Id 2147483728, Number of TR required = 1
[C7x_1 ] 103.833941 s: ===================================================
[C7x_1 ] 103.833973 s: Link Id 562951564034128, Number of TR required = 2
[C7x_1 ] 103.834002 s: ===================================================
[C7x_1 ] 103.834032 s: Link Id 2147483728, Number of TR required = 1
[C7x_1 ] 103.834059 s: ===================================================
[C7x_1 ] 103.834092 s: Link Id 562951564034128, Number of TR required = 2
[C7x_1 ] 103.834120 s: ===================================================
[C7x_1 ] 103.834151 s: Link Id 2147483728, Number of TR required = 1
[C7x_1 ] 103.834179 s: ===================================================
[C7x_1 ] 103.834200 s: Link Index 2147483728
[C7x_1 ] 103.834222 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 103.834254 s: Link->src-> icnt (dim); 1536 18 (1536) 1 (27648) 1 (0)
[C7x_1 ] 103.834288 s: Link->sink-> icnt (dim); 1536 18 (1536) 1 (27648) 1 (0)
[C7x_1 ] 103.834310 s: srcMemPtr: 1744830464
[C7x_1 ] 103.834327 s: dstMemPtr: 1686110208
[C7x_1 ] 103.834359 s: Link Id 562951564034128, Number of TR required = 2
[C7x_1 ] 103.834388 s: ===================================================
[C7x_1 ] 103.834411 s: Link Index 562951564034128
[C7x_1 ] 103.834434 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 103.834466 s: Link->src-> icnt (dim); 32768 2 (32768) 1 (65536) 1 (0)
[C7x_1 ] 103.834500 s: Link->sink-> icnt (dim); 32768 2 (32768) 1 (65536) 1 (0)
[C7x_1 ] 103.834522 s: srcMemPtr: 1744885760
[C7x_1 ] 103.834539 s: dstMemPtr: 1686220800
[C7x_1 ] 103.834610 s: Link Id 2147483728, Number of TR required = 1
[C7x_1 ] 103.834639 s: ===================================================
[C7x_1 ] 103.834671 s: Link Id 562951564034128, Number of TR required = 2
[C7x_1 ] 103.834699 s: ===================================================
[C7x_1 ] 103.834724 s: Alg Init for Layer # - 6
[C7x_1 ] 103.834761 s: Link Id 2684354656, Number of TR required = 1
[C7x_1 ] 103.834789 s: ===================================================
[C7x_1 ] 103.834819 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 103.834847 s: ===================================================
[C7x_1 ] 103.834877 s: Link Id 2684354656, Number of TR required = 1
[C7x_1 ] 103.834905 s: ===================================================
[C7x_1 ] 103.834933 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 103.834961 s: ===================================================
[C7x_1 ] 103.834992 s: Link Id 2684354656, Number of TR required = 1
[C7x_1 ] 103.835020 s: ===================================================
[C7x_1 ] 103.835040 s: Link Index 2684354656
[C7x_1 ] 103.835063 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 103.835095 s: Link->src-> icnt (dim); 64 1024 (64) 32 (65536) 1 (0)
[C7x_1 ] 103.835128 s: Link->sink-> icnt (dim); 64 1024 (64) 2 (65536) 16 (0)
[C7x_1 ] 103.835150 s: srcMemPtr: 4295362560
[C7x_1 ] 103.835167 s: dstMemPtr: 1686110208
[C7x_1 ] 103.835198 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 103.835225 s: ===================================================
[C7x_1 ] 103.835246 s: Link Index 2768240736
Freeing memory for user provided Net
[C7x_1 ] 103.835269 s: Flow 1 Src Shape: 2 Sink Shape 0
----------------------- TIDL Process with TARGET DATA FLOW ------------------------
[C7x_1 ] 103.835300 s: Link->src-> icnt (dim); 1024 64 (1024) 2 (65536) 16 (0)
[C7x_1 ] 103.835335 s: Link->sink-> icnt (dim); 1024 64 (32768) 32 (1024) 1 (0)
[C7x_1 ] 103.835357 s: srcMemPtr: 1744830464
[C7x_1 ] 103.835374 s: dstMemPtr: 4304096256
[C7x_1 ] 103.835432 s: Link Id 2684354656, Number of TR required = 1
[C7x_1 ] 103.835460 s: ===================================================
[C7x_1 ] 103.835490 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 103.835517 s: ===================================================
[C7x_1 ] 103.835541 s: Alg Init for Layer # - 7
[C7x_1 ] 103.835570 s: Alg Init for Layer # - 8
[C7x_1 ] 103.835614 s: Link Id 3758096512, Number of TR required = 3
[C7x_1 ] 103.835642 s: ===================================================
[C7x_1 ] 103.835671 s: Link Id 3808428160, Number of TR required = 1
[C7x_1 ] 103.835699 s: ===================================================
[C7x_1 ] 103.835728 s: Link Id 3825205376, Number of TR required = 1
[C7x_1 ] 103.835755 s: ===================================================
[C7x_1 ] 103.835783 s: Link Id 3841982592, Number of TR required = 1
[C7x_1 ] 103.835811 s: ===================================================
[C7x_1 ] 103.836185 s: Link Id 3758096512, Number of TR required = 3
[C7x_1 ] 103.836214 s: ===================================================
[C7x_1 ] 103.836243 s: Link Id 3808428160, Number of TR required = 1
[C7x_1 ] 103.836271 s: ===================================================
[C7x_1 ] 103.836300 s: Link Id 3825205376, Number of TR required = 1
[C7x_1 ] 103.836327 s: ===================================================
[C7x_1 ] 103.836356 s: Link Id 3841982592, Number of TR required = 1
[C7x_1 ] 103.836384 s: ===================================================
[C7x_1 ] 103.836694 s: Link Id 3758096512, Number of TR required = 3
[C7x_1 ] 103.836722 s: ===================================================
[C7x_1 ] 103.836752 s: Link Id 3808428160, Number of TR required = 1
[C7x_1 ] 103.836779 s: ===================================================
[C7x_1 ] 103.836809 s: Link Id 3825205376, Number of TR required = 1
[C7x_1 ] 103.836836 s: ===================================================
[C7x_1 ] 103.836865 s: Link Id 3841982592, Number of TR required = 1
[C7x_1 ] 103.836892 s: ===================================================
[C7x_1 ] 103.837200 s: Link Id 3758096512, Number of TR required = 3
[C7x_1 ] 103.837228 s: ===================================================
[C7x_1 ] 103.837250 s: Link Index 3758096512
[C7x_1 ] 103.837273 s: Flow 0 Src Shape: 0 Sink Shape 0
[C7x_1 ] 103.837304 s: Link->src-> icnt (dim); 513 128 (16384) 1 (513) 1 (0)
[C7x_1 ] 103.837338 s: Link->sink-> icnt (dim); 513 128 (1056) 1 (513) 1 (0)
[C7x_1 ] 103.837360 s: srcMemPtr: 4304096256
[C7x_1 ] 103.837377 s: dstMemPtr: 1686110336
[C7x_1 ] 103.837401 s: Flow 1 Src Shape: 0 Sink Shape 0
[C7x_1 ] 103.837435 s: Link->src-> icnt (dim); 384 128 (16384) 41 (384) 1 (2097152)
[C7x_1 ] 103.837469 s: Link->sink-> icnt (dim); 384 128 (1056) 41 (384) 1 (0)
[C7x_1 ] 103.837491 s: srcMemPtr: 4304096256
[C7x_1 ] 103.837508 s: dstMemPtr: 1686110336
[C7x_1 ] 103.837531 s: Flow 2 Src Shape: 0 Sink Shape 0
[C7x_1 ] 103.837562 s: Link->src-> icnt (dim); 127 128 (16384) 1 (384) 1 (0)
[C7x_1 ] 103.837595 s: Link->sink-> icnt (dim); 127 128 (1056) 1 (384) 1 (0)
[C7x_1 ] 103.837616 s: srcMemPtr: 4304097282
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoef,
[C7x_1 ] 103.837634 s: dstMemPtr: 1686111362
[C7x_1 ] 103.837662 s: Link Id 3808428160, Number of TR required = 1
2, 55574, 6403, 8911, 8633, 8258, 0, 0, ,
[C7x_1 ] 103.837689 s: ===================================================
4, 39202, 2936, 4484, 7073, 1808, 0, 0, ,
[C7x_1 ] 103.837710 s: Link Index 3808428160
3, 63718, 10829, 12256, 8940, 17675, 0, 0, ,
[C7x_1 ] 103.837733 s: Flow 1 Src Shape: 0 Sink Shape 2
5, 1793977, 1753101, 1754811, 8713, 4129, 0, 0, ,
[C7x_1 ] 103.837764 s: Link->src-> icnt (dim); 1152 32 (1188) 8 (38016) 1 (0)
6, 343405, 155631, 304934, 7726, 5762, 0, 0, ,
[C7x_1 ] 103.837798 s: Link->sink-> icnt (dim); 1152 32 (1184) 2 (37888) 4 (0)
7, 23029, 0, 0, 0, 0, 0, 0, ,
[C7x_1 ] 103.837820 s: srcMemPtr: 1745545216
8, 6725707, 5846896, 6669420, 21161, 10641, 0, 0, ,
[C7x_1 ] 103.837838 s: dstMemPtr: 1686411904
9, 819583, 289935, 783583, 8270, 3376, 0, 0, ,
Sum of Layer Cycles 9864195
[C7x_1 ] 103.837866 s: Link Id 3825205376, Number of TR required = 1
[C7x_1 ] 103.837893 s: ===================================================
[C7x_1 ] 103.837914 s: Link Index 3825205376
[C7x_1 ] 103.837937 s: Flow 1 Src Shape: 0 Sink Shape 0
[C7x_1 ] 103.837966 s: Link->src-> icnt (dim); 4 256 (4) 1 (4) 1 (1024)
[C7x_1 ] 103.837997 s: Link->sink-> icnt (dim); 4 256 (4) 1 (4) 1 (0)
[C7x_1 ] 103.838017 s: srcMemPtr: 4432208384
[C7x_1 ] 103.838034 s: dstMemPtr: 1686563456
[C7x_1 ] 103.838062 s: Link Id 3841982592, Number of TR required = 1
[C7x_1 ] 103.838090 s: ===================================================
# NETWORK_EXECUTION_TIME = 12.26 (in ms, c7x @1GHz) with DDR_BANDWIDTH (Read + Write) = 69.24, 39.60, 108.84 (in Mega Bytes/
...[C7x_1 ] 103.838133 s: Flow 1 Src Shape: 2 Sink Shape 0
[C7x_1 ] 103.838164 s: Link->src-> icnt (dim); 384 32 (416) 2 (13312) 172 (0)
[C7x_1 ] 103.838199 s: Link->sink-> icnt (dim); 384 32 (17056) 8 (545792) 43 (384)
[C7x_1 ] 103.838221 s: srcMemPtr: 1745438720
[C7x_1 ] 103.838239 s: dstMemPtr: 4295362560
[C7x_1 ] 103.840050 s: Start Layer Idx 8
[C7x_1 ] 103.840075 s: kerInitArgs->funcStyle 1
[C7x_1 ] 103.840099 s: kerInitArgs->No 256
[C7x_1 ] 103.840121 s: kerInitArgs->inChOffset 1056
[C7x_1 ] 103.840144 s: kerInitArgs->validColsIn 513
[C7x_1 ] 103.840167 s: kerInitArgs->validColsPerRowIn 0
[C7x_1 ] 103.840188 s: kerInitArgs->validRowsIn 0
[C7x_1 ] 103.840211 s: kerInitArgs->inputPitchPerRow 256
[C7x_1 ] 103.840234 s: kerInitArgs->outputPitchPerRow 256
[C7x_1 ] 103.840257 s: kerInitArgs->inWidth 128
[C7x_1 ] 103.840279 s: kerInitArgs->pad 0
[C7x_1 ] 103.840301 s: kerInitArgs->maxHeight 128
[C7x_1 ] 103.840323 s: kerInitArgs->subMChannels 32
[C7x_1 ] 103.840345 s: kerInitArgs->Fr 3
[C7x_1 ] 103.840367 s: kerInitArgs->Fc 3
[C7x_1 ] 103.840389 s: kerInitArgs->strideX 1
[C7x_1 ] 103.840410 s: kerInitArgs->strideY 1
[C7x_1 ] 103.840444 s: kerInitArgs->dilationX 1
[C7x_1 ] 103.840467 s: kerInitArgs->dilationY 1
[C7x_1 ] 103.840489 s: kerInitArgs->bias 32767
[C7x_1 ] 103.840511 s: kerInitArgs->activationType 2
[C7x_1 ] 103.840533 s: kerInitArgs->mode 0
[C7x_1 ] 103.840555 s: src0Addr->data_type 1
[C7x_1 ] 103.840577 s: src0Addr->dim_x 1152
[C7x_1 ] 103.840599 s: src0Addr->dim_y 32
[C7x_1 ] 103.840622 s: src0Addr->stride_y 2368
[C7x_1 ] 103.840644 s: src1Addr->data_type 1
[C7x_1 ] 103.840666 s: src1Addr->dim_x 642
[C7x_1 ] 103.840689 s: src1Addr->dim_y 128
[C7x_1 ] 103.840712 s: src1Addr->stride_y 2112
[C7x_1 ] 103.840734 s: dstAddr->data_type 1
[C7x_1 ] 103.840756 s: dstAddr->dim_x 384
[C7x_1 ] 103.840778 s: dstAddr->dim_y 32
[C7x_1 ] 103.840801 s: dstAddr->stride_y 832
[C7x_1 ] 103.840818 s: End Layer Idx 8
[C7x_1 ] 103.841260 s: Not enough memory to allocate intMemPtr in MSMC
[C7x_1 ] 103.841299 s: Warning: Trying to get scratch mem from DDR. Expect performance degradation!
[C7x_1 ] 103.841333 s: Link Id 3758096512, Number of TR required = 3
[C7x_1 ] 103.841361 s: ===================================================
[C7x_1 ] 103.841391 s: Link Id 3808428160, Number of TR required = 1
[C7x_1 ] 103.841419 s: ===================================================
[C7x_1 ] 103.841447 s: Link Id 3825205376, Number of TR required = 1
[C7x_1 ] 103.841475 s: ===================================================
[C7x_1 ] 103.841504 s: Link Id 3841982592, Number of TR required = 1
[C7x_1 ] 103.841836 s: Alg Init for Layer # - 9
[C7x_1 ] 105.184129 s: TIDL_process is started with handle : 100000000
[C7x_1 ] 105.184171 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256 is serviced
[C7x_1 ] 105.184218 s: PREEMPTION: Requesting LOCK for priroty object with handle = 100000000 and targetPriority 256
[C7x_1 ] 105.184273 s: PREEMPTION: Request of LOCK for priroty object with handle = 100000000 and targetPriority 256 is serviced wit0
....[C7x_1 ] 105.184371 s: TIDL_activate is called with handle : 100000000 - Copying handle of size 20144 from 100000000 to 682d200
[C7x_1 ] 105.184457 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256
[C7x_1 ] 105.184499 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256 is serviced
[C7x_1 ] 105.184545 s: PREEMPTION: Requesting LOCK for priroty object with handle = 100000000 and targetPriority 256
[C7x_1 ] 105.184599 s: PREEMPTION: Request of LOCK for priroty object with handle = 100000000 and targetPriority 256 is serviced wit0
[C7x_1 ] 105.184633 s: Coreid 0 Layerid to execute = 2
[C7x_1 ] 105.184662 s: Core 0 Alg Process for Layer # - 2, layer type 29
[C7x_1 ] 105.184689 s: Processing Layer # - 2
[C7x_1 ] 105.184752 s: Core 0 End of Layer # - 2 with outPtrs[0] = 6800d800
[C7x_1 ] 105.184783 s: Coreid 0 Layerid to execute = 4
[C7x_1 ] 105.184812 s: Core 0 Alg Process for Layer # - 4, layer type 41
[C7x_1 ] 105.184837 s: Processing Layer # - 4
[C7x_1 ] 105.184885 s: Core 0 End of Layer # - 4 with outPtrs[0] = 68000000
[C7x_1 ] 105.184913 s: Coreid 0 Layerid to execute = 3
[C7x_1 ] 105.184941 s: Core 0 Alg Process for Layer # - 3, layer type 29
[C7x_1 ] 105.184967 s: Processing Layer # - 3
.....[C7x_1 ] 105.185039 s: Core 0 End of Layer # - 3 with outPtrs[0] = 6800d800
[C7x_1 ] 105.185067 s: Coreid 0 Layerid to execute = 5
[C7x_1 ] 105.185095 s: Core 0 Alg Process for Layer # - 5, layer type 43
[C7x_1 ] 105.185119 s: Processing Layer # - 5
[C7x_1 ] 105.186923 s: Core 0 End of Layer # - 5 with outPtrs[0] = 100060800
[C7x_1 ] 105.186952 s: Coreid 0 Layerid to execute = 6
[C7x_1 ] 105.186982 s: Core 0 Alg Process for Layer # - 6, layer type 41
[C7x_1 ] 105.187007 s: Processing Layer # - 6
[C7x_1 ] 105.187359 s: Core 0 End of Layer # - 6 with outPtrs[0] = 1008b4c00
[C7x_1 ] 105.187387 s: Coreid 0 Layerid to execute = 7
[C7x_1 ] 105.187416 s: Core 0 Alg Process for Layer # - 7, layer type 38
[C7x_1 ] 105.187440 s: Processing Layer # - 7
[C7x_1 ] 105.187471 s: Core 0 End of Layer # - 7 with outPtrs[0] = 1008b4c00
[C7x_1 ] 105.187497 s: Coreid 0 Layerid to execute = 8
[C7x_1 ] 105.187526 s: Core 0 Alg Process for Layer # - 8, layer type 1
[C7x_1 ] 105.187550 s: Processing Layer # - 8
[C7x_1 ] 105.194287 s: Core 0 End of Layer # - 8 with outPtrs[0] = 100060800
[C7x_1 ] 105.194317 s: Coreid 0 Layerid to execute = 9
[C7x_1 ] 105.194346 s: Core 0 Alg Process for Layer # - 9, layer type 29
[C7x_1 ] 105.194371 s: Processing Layer # - 9
[C7x_1 ] 105.195199 s: Core 0 End of Layer # - 9 with outPtrs[0] = c030b000
[C7x_1 ] 105.195227 s: Coreid 0 Layerid to execute = -1
[C7x_1 ] 105.195262 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256
[C7x_1 ] 105.195308 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256 is serviced
[C7x_1 ] 105.195354 s: PREEMPTION: Requesting LOCK for priroty object with handle = 100000000 and targetPriority 256
[C7x_1 ] 105.195409 s: PREEMPTION: Request of LOCK for priroty object with handle = 100000000 and targetPriority 256 is serviced wit0
[C7x_1 ] 105.195453 s: TIDL_process is completed with handle : 100000000
[C7x_1 ] 105.195492 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256
[C7x_1 ] 105.195535 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256 is serviced
[C7x_1 ] 106.199925 s: TIDL_deactivate is called with handle : 100000000 - Copying handle of size 20144 from 682d2000 to 100000000
APP: Deinit ... !!!
REMOTE_SERVICE: Deinit ... !!!
[C7x_1 ] 106.200041 s: PREEMPTION: Removing priroty object with handle = 100000000 and targetPriority = 256, Number of obejcts 6
REMOTE_SERVICE: Deinit ... Done !!!
106.539062 s: IPC: Deinit ... !!!
106.539875 s: IPC: DeInit ... Done !!!
106.539896 s: MEM: Deinit ... !!!
106.539906 s: DDR_SHARED_MEM: Alloc's: 8 alloc's of 20016464 bytes
106.539914 s: DDR_SHARED_MEM: Free's : 8 free's of 20016464 bytes
106.539921 s: DDR_SHARED_MEM: Open's : 0 allocs of 0 bytes
106.539933 s: MEM: Deinit ... Done !!!
APP: Deinit ... Done !!!
root@j784s4-evm:/opt/0711_simple_demo2#
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Offline | ttyUSB0
import log:
/home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/tidl_model_import.out tidl_config.txt
more than one value provided for SINGLE parameter 'foldPreBnConv2D' - picking up only first value
more than one value provided for SINGLE parameter 'numFrames' - picking up only first value
more than one value provided for SINGLE parameter 'foldPreBnConv2D' - picking up only first value
more than one value provided for SINGLE parameter 'numFrames' - picking up only first value========================= [Model Compilation Started] =========================
Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning
============================== [Version Summary] ==============================
-------------------------------------------------------------------------------
| TIDL Tools Version | 11_00_08_00 |
-------------------------------------------------------------------------------
| C7x Firmware Version | 11_00_00_00 |
-------------------------------------------------------------------------------
ONNX model (Proto) file : SimpleBev_OD.onnx
TIDL network file : output/tidl_net.bin
TIDL IO info file : output/tidl_io_
Current ONNX OpSet version : 16
============================ [Optimization started] ============================
Running tidl_optimizeNet
S.No,Layer Type,Output Data,Out Id,Input Data,In IDs,
0,TIDL_DataLayer,/bev_encoder/Reshape_15_output_0,0,,
1,TIDL_DataLayer,/bev_encoder/Unsqueeze_5_output_0,1,,
2,TIDL_GridSampleLayer,/bev_encoder/GridSample_5_output_0,2,/bev_encoder/Reshape_15_output_0 |/bev_encoder/Unsqueeze_5_output_0 |,0 |1 |
3,TIDL_ReshapeLayer,/bev_encoder/Reshape_18_output_0,3,/bev_encoder/GridSample_5_output_0 |,2 |
4,TIDL_ConvolutionLayer,/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0,4,/bev_encoder/Reshape_18_output_0 |,3 |
5,TIDL_DataLayer,/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0,0,/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0 |,4 |
----------------------------- Optimization Summary -----------------------------
--------------------------------------------------------------------------------
| Layer | Nodes before optimization | Nodes after optimization |
--------------------------------------------------------------------------------
| TIDL_TransposeLayer | 0 | 2 |
| TIDL_ConvolutionLayer | 1 | 1 |
| TIDL_GridSampleLayer | 1 | 1 |
--------------------------------------------------------------------------------
Total nodes in subgraph: 8
--------------------- Layer mapping to TIDL Network Layers ---------------------
------------------------------------------------------------------------------------------------------------------
| Layer Outputs Before Optimization | Layer Outputs After Optimization |
------------------------------------------------------------------------------------------------------------------
| /bev_encoder/GridSample_5_output_0 | /bev_encoder/Reshape_15_output_0_0, /bev_encoder/GridSample_5_output_0_1, |
| | /bev_encoder/GridSample_5_output_0 |
------------------------------------------------------------------------------------------------------------------
Completed tidl_optimizeNet
=========================== [Optimization completed] ===========================
Empty prototxt path, running calibration
Num of Layer Detected : 8
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num|TIDL Layer Name |Out Data Name |Group |#Ins |#Outs |Inbuf Ids |Outbuf Id |In NCHW |Out NCHW |MACS |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0|TIDL_DataLayer |/bev_encoder/Reshape_15_output_0 | 0| -1| 1| x x x x x x x x | 0 | 0 0 0 0 0 0 | 1 1 1 64 18 24 | 0 |
1|TIDL_DataLayer |/bev_encoder/Unsqueeze_5_output_0 | 0| -1| 1| x x x x x x x x | 1 | 0 0 0 0 0 0 | 1 1 1 1 32768 2 | 0 |
2|TIDL_TransposeLayer |/bev_encoder/Reshape_15_output_0_0 | 0| 1| 1| 0 x x x x x x x | 2 | 1 1 1 64 18 24 | 1 1 1 18 24 64 | 27648 |
3|TIDL_GridSampleLayer |/bev_encoder/GridSample_5_output_0_1 | 0| 2| 1| 2 1 x x x x x x | 3 | 1 1 1 18 24 64 | 1 1 1 1 32768 64 | 2097152 |
4|TIDL_TransposeLayer |/bev_encoder/GridSample_5_output_0 | 0| 1| 1| 3 x x x x x x x | 4 | 1 1 1 1 32768 64 | 1 1 1 64 1 32768 | 2097152 |
5|TIDL_ReshapeLayer |/bev_encoder/Reshape_18_output_0 | 0| 1| 1| 4 x x x x x x x | 5 | 1 1 1 64 1 32768 | 1 1 1 128 128 128 | 0 |
6|TIDL_ConvolutionLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| 1| 5 x x x x x x x | 6 | 1 1 1 128 128 128 | 1 1 1 256 128 128 |4831838208 |
7|TIDL_DataLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| -1| 6 x x x x x x x | 0 | 1 1 1 256 128 128 | 0 0 0 0 0 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 4.8361
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num of Layer Detected : 8
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num|TIDL Layer Name |Out Data Name |Group |#Ins |#Outs |Inbuf Ids |Outbuf Id |In NCHW |Out NCHW |MACS |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0|TIDL_DataLayer |/bev_encoder/Reshape_15_output_0 | 0| -1| 1| x x x x x x x x | 0 | 0 0 0 0 0 0 | 1 1 1 64 18 24 | 0 |
1|TIDL_DataLayer |/bev_encoder/Unsqueeze_5_output_0 | 0| -1| 1| x x x x x x x x | 1 | 0 0 0 0 0 0 | 1 1 1 1 32768 2 | 0 |
2|TIDL_TransposeLayer |/bev_encoder/Reshape_15_output_0_0 | 0| 1| 1| 0 x x x x x x x | 2 | 1 1 1 64 18 24 | 1 1 1 18 24 64 | 27648 |
3|TIDL_GridSampleLayer |/bev_encoder/GridSample_5_output_0_1 | 0| 2| 1| 2 1 x x x x x x | 3 | 1 1 1 18 24 64 | 1 1 1 1 32768 64 | 2097152 |
4|TIDL_TransposeLayer |/bev_encoder/GridSample_5_output_0 | 0| 1| 1| 3 x x x x x x x | 4 | 1 1 1 1 32768 64 | 1 1 1 64 1 32768 | 2097152 |
5|TIDL_ReshapeLayer |/bev_encoder/Reshape_18_output_0 | 0| 1| 1| 4 x x x x x x x | 5 | 1 1 1 64 1 32768 | 1 1 1 128 128 128 | 0 |
6|TIDL_ConvolutionLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| 1| 5 x x x x x x x | 6 | 1 1 1 128 128 128 | 1 1 1 256 128 128 |4831838208 |
7|TIDL_DataLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| -1| 6 x x x x x x x | 0 | 1 1 1 256 128 128 | 0 0 0 0 0 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 4.8361
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
cd /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools && ./PC_dsp_test_dl_algo.out s:/home/ht/customers/xxxx/0711_simple_demo2/output/tidl_config.txt.qunat_stats_config.txt
Input : dataId=0, name=/bev_encoder/Reshape_15_output_0, elementType 6, scale=16.000000, zero point=0, layout=0
Input : dataId=1, name=/bev_encoder/Unsqueeze_5_output_0, elementType 6, scale=16384.000000, zero point=0, layout=0
Ouput : dataId=6, name=/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0, elementType 6, scale=1.000000, zero point=0, layout=0
144423488, 137.733 0x797860223010
worstCaseDelay for Pre-emption is 0.0000000
Network File Read done
Calling algAlloc
TIDL_initDebugTraceParams Done
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.67 , 0x00000000
1 , DDR Cacheable , Persistent , 128, 0.66 , 0x00000000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x00000000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x00000000
5 , DDR Cacheable , Persistent , 128, 259.38 , 0x00000000
6 , DDR Cacheable , Scratch , 128, 24943.00, 0x00000000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x00000000
8 , DDR Cacheable , Scratch , 128, 24576.12, 0x00000000
9 , DDR Cacheable , Scratch , 128, 32771.00, 0x00000000
10 , DDR Cacheable , Persistent , 128, 293.47 , 0x00000000
11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x00000000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
13 , DDR Cacheable , Persistent , 128, 141038.69, 0x00000000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000
15 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 228074.61
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Num, Space, SizeinBytes, SineInMB
0, 17, 20144, 0.019 0x5b52cf4c2880
1, 17, 672, 0.001 0x5b52cf4c7800
2, 17, 16384, 0.016 0x5b52cf4c7b80
3, 17, 4096, 0.004 0x5b52cf4cbc00
4, 17, 57344, 0.055 0x5b52cf4ccd00
5, 17, 265600, 0.253 0x7978fcc9e080
6, 17, 25541632, 24.358 0x79785e9c7080
7, 17, 128, 0.000 0x5b52cf4c1700
8, 17, 25165952, 24.000 0x79785d1c6080
9, 17, 33557504, 32.003 0x79785b1c5080
10, 17, 300512, 0.287 0x7978fcc54080
11, 17, 4194560, 4.000 0x79785adc4080
12, 17, 128, 0.000 0x5b52cf4c1800
13, 17, 144423616, 137.733 0x797852408080
14, 17, 1, 0.000 0x5b52cf4dad80
15, 17, 128, 0.000 0x5b52cf4dae80
Total External Memory (DDR) Size = 233548401, 222.729
TIDL init call from ivision API
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.67 , 0xcf4c2880
1 , DDR Cacheable , Persistent , 128, 0.66 , 0xcf4c7800
2 , DDR Cacheable , Scratch , 128, 16.00 , 0xcf4c7b80
3 , DDR Cacheable , Scratch , 128, 4.00 , 0xcf4cbc00
4 , DDR Cacheable , Scratch , 128, 56.00 , 0xcf4ccd00
5 , DDR Cacheable , Persistent , 128, 259.38 , 0xfcc9e080
6 , DDR Cacheable , Scratch , 128, 24943.00, 0x5e9c7080
7 , DDR Cacheable , Scratch , 128, 0.12 , 0xcf4c1700
8 , DDR Cacheable , Scratch , 128, 24576.12, 0x5d1c6080
9 , DDR Cacheable , Scratch , 128, 32771.00, 0x5b1c5080
10 , DDR Cacheable , Persistent , 128, 293.47 , 0xfcc54080
11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x5adc4080
12 , DDR Cacheable , Persistent , 128, 0.12 , 0xcf4c1800
13 , DDR Cacheable , Persistent , 128, 141038.69, 0x52408080
14 , DDR Cacheable , Persistent , 128, 0.00 , 0xcf4dad80
15 , DDR Cacheable , Persistent , 128, 0.12 , 0xcf4dae80
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 228074.61
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Alg Init for Layer # - 2
Alg Init for Layer # - 3
Alg Init for Layer # - 4
Alg Init for Layer # - 5
Alg Init for Layer # - 6
Freeing memory for user provided Net
Instance created for /home/ht/customers/xxxx/0711_simple_demo2/output/tidl_config.txt.qunat_stats_config.txt
Processing Cnt : 0, InstCnt : 0 /home/ht/customers/xxxx/0711_simple_demo2/output/tidl_net.bin!
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
Warning :: File read for binary data load is not suffcient in size to fill the input tensor, Filling it with zero
224640, 0.214 0x797867ba7080
1048576, 1.000 0x797867aa6080
67371008, 64.250 0x797863a65080
Skipping static gen-set function==============================================] 100 %
TIDL_process is started with handle : 0x5b52cf4c2880
TIDL_activate is called with handle : 0x5b52cf4c2880 - Copying handle of size 20144 from 0x5b52cf4c2880 to 0x5b52cf4ccd80
Coreid 0 Layerid to execute = 0
Core 0 Alg Process for Layer # - 0, layer type 0
Coreid 0 Layerid to execute = 1
Core 0 Alg Process for Layer # - 1, layer type 0
Coreid 0 Layerid to execute = 2
Core 0 Alg Process for Layer # - 2, layer type 41
Processing Layer # - 2
Core 0 End of Layer # - 2 with outPtrs[0] = 0x79785e9c7080
Coreid 0 Layerid to execute = 3
Core 0 Alg Process for Layer # - 3, layer type 43
Processing Layer # - 3
Core 0 End of Layer # - 3 with outPtrs[0] = 0x79785e9e2100
Coreid 0 Layerid to execute = 4
Core 0 Alg Process for Layer # - 4, layer type 41
Processing Layer # - 4
Core 0 End of Layer # - 4 with outPtrs[0] = 0x79785f1e2180
Coreid 0 Layerid to execute = 5
Core 0 Alg Process for Layer # - 5, layer type 38
Processing Layer # - 5
Core 0 End of Layer # - 5 with outPtrs[0] = 0x79785f9e2200
Coreid 0 Layerid to execute = 6
Core 0 Alg Process for Layer # - 6, layer type 1
Processing Layer # - 6
Core 0 End of Layer # - 6 with outPtrs[0] = 0x797863a65080
Coreid 0 Layerid to execute = 7
Core 0 Alg Process for Layer # - 7, layer type 0
Coreid 0 Layerid to execute = -1
TIDL_process is completed with handle : 0x5b52cf4c2880
Skipping static gen-set function
TIDL_deactivate is called with handle : 0x5b52cf4c2880 - Copying handle of size 20144 from 0x5b52cf4ccd80 to 0x5b52cf4c2880
------------------ Fixed-point Calibration Iteration [1 / 1]: ------------------
Empty prototxt path, running calibration
Num of Layer Detected : 8
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num|TIDL Layer Name |Out Data Name |Group |#Ins |#Outs |Inbuf Ids |Outbuf Id |In NCHW |Out NCHW |MACS |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0|TIDL_DataLayer |/bev_encoder/Reshape_15_output_0 | 0| -1| 1| x x x x x x x x | 0 | 0 0 0 0 0 0 | 1 1 1 64 18 24 | 0 |
1|TIDL_DataLayer |/bev_encoder/Unsqueeze_5_output_0 | 0| -1| 1| x x x x x x x x | 1 | 0 0 0 0 0 0 | 1 1 1 1 32768 2 | 0 |
2|TIDL_TransposeLayer |/bev_encoder/Reshape_15_output_0_0 | 0| 1| 1| 0 x x x x x x x | 2 | 1 1 1 64 18 24 | 1 1 1 18 24 64 | 27648 |
3|TIDL_GridSampleLayer |/bev_encoder/GridSample_5_output_0_1 | 0| 2| 1| 2 1 x x x x x x | 3 | 1 1 1 18 24 64 | 1 1 1 1 32768 64 | 2097152 |
4|TIDL_TransposeLayer |/bev_encoder/GridSample_5_output_0 | 0| 1| 1| 3 x x x x x x x | 4 | 1 1 1 1 32768 64 | 1 1 1 64 1 32768 | 2097152 |
5|TIDL_ReshapeLayer |/bev_encoder/Reshape_18_output_0 | 0| 1| 1| 4 x x x x x x x | 5 | 1 1 1 64 1 32768 | 1 1 1 128 128 128 | 0 |
6|TIDL_ConvolutionLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| 1| 5 x x x x x x x | 6 | 1 1 1 128 128 128 | 1 1 1 256 128 128 |4831838208 |
7|TIDL_DataLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| -1| 6 x x x x x x x | 0 | 1 1 1 256 128 128 | 0 0 0 0 0 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 4.8361
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
cd /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools && ./PC_dsp_test_dl_algo.out s:/home/ht/customers/xxxx/0711_simple_demo2/output/tidl_config.txt.qunat_stats_config.txt
Input : dataId=0, name=/bev_encoder/Reshape_15_output_0, elementType 1, scale=16.000000, zero point=0, layout=0
Input : dataId=1, name=/bev_encoder/Unsqueeze_5_output_0, elementType 3, scale=16384.000000, zero point=0, layout=0
Ouput : dataId=6, name=/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0, elementType 3, scale=1024.000000, zero point=0, layout=0
143833152, 137.170 0x7095b2eb3010
worstCaseDelay for Pre-emption is 0.0000000
Network File Read done
Calling algAlloc
TIDL_initDebugTraceParams Done
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.67 , 0x00000000
1 , DDR Cacheable , Persistent , 128, 0.66 , 0x00000000
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x00000000
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x00000000
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x00000000
5 , DDR Cacheable , Persistent , 128, 260.38 , 0x00000000
6 , DDR Cacheable , Scratch , 128, 6236.88 , 0x00000000
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x00000000
8 , DDR Cacheable , Scratch , 128, 49152.12, 0x00000000
9 , DDR Cacheable , Scratch , 128, 16387.00, 0x00000000
10 , DDR Cacheable , Persistent , 128, 293.47 , 0x00000000
11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x00000000
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
13 , DDR Cacheable , Persistent , 128, 140462.19, 0x00000000
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x00000000
15 , DDR Cacheable , Persistent , 128, 0.12 , 0x00000000
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 216984.98
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Num, Space, SizeinBytes, SineInMB
0, 17, 20144, 0.019 0x62d41704f480
1, 17, 672, 0.001 0x62d417054400
2, 17, 16384, 0.016 0x62d417054780
3, 17, 4096, 0.004 0x62d417058880
4, 17, 57344, 0.055 0x62d417059900
5, 17, 266624, 0.254 0x70964f86e080
6, 17, 6386560, 6.091 0x7095b289b080
7, 17, 128, 0.000 0x62d41704e300
8, 17, 50331776, 48.000 0x7095af89a080
9, 17, 16780288, 16.003 0x7095ae899080
10, 17, 300512, 0.287 0x70964f4c5080
11, 17, 4194560, 4.000 0x7095ae498080
12, 17, 128, 0.000 0x62d41704e480
13, 17, 143833280, 137.170 0x7095a5b6c080
14, 17, 1, 0.000 0x62d417067a00
15, 17, 128, 0.000 0x62d417067a80
Total External Memory (DDR) Size = 222192625, 211.899
TIDL init call from ivision API
--------------------------------------------
TIDL Memory size requiement (record wise):
MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
0 , DDR Cacheable , Persistent , 128, 19.67 , 0x1704f480
1 , DDR Cacheable , Persistent , 128, 0.66 , 0x17054400
2 , DDR Cacheable , Scratch , 128, 16.00 , 0x17054780
3 , DDR Cacheable , Scratch , 128, 4.00 , 0x17058880
4 , DDR Cacheable , Scratch , 128, 56.00 , 0x17059900
5 , DDR Cacheable , Persistent , 128, 260.38 , 0x4f86e080
6 , DDR Cacheable , Scratch , 128, 6236.88 , 0xb289b080
7 , DDR Cacheable , Scratch , 128, 0.12 , 0x1704e300
8 , DDR Cacheable , Scratch , 128, 49152.12, 0xaf89a080
9 , DDR Cacheable , Scratch , 128, 16387.00, 0xae899080
10 , DDR Cacheable , Persistent , 128, 293.47 , 0x4f4c5080
11 , DDR Cacheable , Scratch , 128, 4096.25 , 0xae498080
12 , DDR Cacheable , Persistent , 128, 0.12 , 0x1704e480
13 , DDR Cacheable , Persistent , 128, 140462.19, 0xa5b6c080
14 , DDR Cacheable , Persistent , 128, 0.00 , 0x17067a00
15 , DDR Cacheable , Persistent , 128, 0.12 , 0x17067a80
--------------------------------------------
Total memory size requirement (space wise):
Mem Space , Size(KBytes)
DDR Cacheable, 216984.98
--------------------------------------------
NOTE: Memory requirement in host emulation can be different from the same on EVM
To get the actual TIDL memory requirement make sure to run on EVM with
debugTraceLevel = 2
--------------------------------------------
Alg Init for Layer # - 2
Alg Init for Layer # - 3
Alg Init for Layer # - 4
Alg Init for Layer # - 5
Alg Init for Layer # - 6
Freeing memory for user provided Net
Instance created for /home/ht/customers/xxxx/0711_simple_demo2/output/tidl_config.txt.qunat_stats_config.txt
Processing Cnt : 0, InstCnt : 0 /home/ht/customers/xxxx/0711_simple_demo2/output/tidl_net.bin!
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
TIDL_RT: Set default TIDLRT tensor done
Warning :: File read for binary data load is not suffcient in size to fill the input tensor, Filling it with zero
56160, 0.054 0x62d417078300
524288, 0.500 0x7095baf5d080
16842752, 16.062 0x7095b9f4c080
Skipping static gen-set function==============================================] 100 %
TIDL_process is started with handle : 0x62d41704f480
TIDL_activate is called with handle : 0x62d41704f480 - Copying handle of size 20144 from 0x62d41704f480 to 0x62d417059980
Coreid 0 Layerid to execute = 0
Core 0 Alg Process for Layer # - 0, layer type 0
Coreid 0 Layerid to execute = 1
Core 0 Alg Process for Layer # - 1, layer type 0
Coreid 0 Layerid to execute = 2
Core 0 Alg Process for Layer # - 2, layer type 41
Processing Layer # - 2
Core 0 End of Layer # - 2 with outPtrs[0] = 0x7095b289b080
Coreid 0 Layerid to execute = 3
Core 0 Alg Process for Layer # - 3, layer type 43
Processing Layer # - 3
Core 0 End of Layer # - 3 with outPtrs[0] = 0x7095b28a1d00
Coreid 0 Layerid to execute = 4
Core 0 Alg Process for Layer # - 4, layer type 41
Processing Layer # - 4
Core 0 End of Layer # - 4 with outPtrs[0] = 0x7095b2aa1d80
Coreid 0 Layerid to execute = 5
Core 0 Alg Process for Layer # - 5, layer type 38
Processing Layer # - 5
Core 0 End of Layer # - 5 with outPtrs[0] = 0x7095b2ca1e00
Coreid 0 Layerid to execute = 6
Core 0 Alg Process for Layer # - 6, layer type 1
Processing Layer # - 6
Core 0 End of Layer # - 6 with outPtrs[0] = 0x7095b9f4c080
Coreid 0 Layerid to execute = 7
Core 0 Alg Process for Layer # - 7, layer type 0
Coreid 0 Layerid to execute = -1
TIDL_process is completed with handle : 0x62d41704f480
Skipping static gen-set function
TIDL_deactivate is called with handle : 0x62d41704f480 - Copying handle of size 20144 from 0x62d417059980 to 0x62d41704f480
Empty prototxt path, running calibration
Num of Layer Detected : 8
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Num|TIDL Layer Name |Out Data Name |Group |#Ins |#Outs |Inbuf Ids |Outbuf Id |In NCHW |Out NCHW |MACS |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
0|TIDL_DataLayer |/bev_encoder/Reshape_15_output_0 | 0| -1| 1| x x x x x x x x | 0 | 0 0 0 0 0 0 | 1 1 1 64 18 24 | 0 |
1|TIDL_DataLayer |/bev_encoder/Unsqueeze_5_output_0 | 0| -1| 1| x x x x x x x x | 1 | 0 0 0 0 0 0 | 1 1 1 1 32768 2 | 0 |
2|TIDL_TransposeLayer |/bev_encoder/Reshape_15_output_0_0 | 0| 1| 1| 0 x x x x x x x | 2 | 1 1 1 64 18 24 | 1 1 1 18 24 64 | 27648 |
3|TIDL_GridSampleLayer |/bev_encoder/GridSample_5_output_0_1 | 0| 2| 1| 2 1 x x x x x x | 3 | 1 1 1 18 24 64 | 1 1 1 1 32768 64 | 2097152 |
4|TIDL_TransposeLayer |/bev_encoder/GridSample_5_output_0 | 0| 1| 1| 3 x x x x x x x | 4 | 1 1 1 1 32768 64 | 1 1 1 64 1 32768 | 2097152 |
5|TIDL_ReshapeLayer |/bev_encoder/Reshape_18_output_0 | 0| 1| 1| 4 x x x x x x x | 5 | 1 1 1 64 1 32768 | 1 1 1 128 128 128 | 0 |
6|TIDL_ConvolutionLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| 1| 5 x x x x x x x | 6 | 1 1 1 128 128 128 | 1 1 1 256 128 128 |4831838208 |
7|TIDL_DataLayer |_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0| 0| 1| -1| 6 x x x x x x x | 0 | 1 1 1 256 128 128 | 0 0 0 0 0 0 | 0 |
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
Total Giga Macs : 4.8361
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
==================== [Quantization & Calibration Completed] ====================
cd /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools && ./ti_cnnperfsim.out /home/ht/customers/xxxx/0711_simple_demo2/output/tidl_config.txt.perf_sim_config.txt /tmp 83887681 0 2
========================== [Memory Planning Started] ==========================
------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation
========================= [Memory Planning Completed] =========================
Network buffer segments:
buf(0), offset( 0), size( 14976)
buf(1), offset( 832320), size( 590336)
buf(2), offset( 14976), size( 817344)
buf(3), offset( 1422656), size( 491484)
Rerunning network compiler...
cd /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools && ./ti_cnnperfsim.out /home/ht/customers/xxxx/0711_simple_demo2/output/tidl_config.txt.perf_sim_config.txt /tmp 83887681 0 2
========================== [Memory Planning Started] ==========================
------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation
========================= [Memory Planning Completed] =========================
Network buffer segments:
buf(0), offset( 0), size( 14976)
buf(1), offset( 832320), size( 590336)
buf(2), offset( 14976), size( 817344)
buf(3), offset( 1422656), size( 491484)
[TIDL Import] WARNING: Couldn't open graphVizTool file: ../../utils/tidlModelGraphviz/out/tidl_graphVisualiser.out . Skipping Graph Visualization.
[TIDL Import] WARNING: Couldn't open graphVizTool file: ../../utils/tidlModelGraphviz/out/tidl_graphVisualiser.out . Skipping Graph Visualization.
****************************************************
** TIDL Model Checker **
****************************************************
======================== Subgraph Compiled Successfully ========================
And I examined your import config and made some modifications:
modelType = 2 numParamBits = 8 numFeatureBits = 8 quantizationStyle = 3 inputNetFile = "SimpleBev_OD.onnx" outputNetFile = "output/tidl_net.bin" outputParamsFile = "output/tidl_io_" inDataNorm = 0 0 inMean = 123.675 116.28 103.53 inScale = 0.01712 0.01750 0.01743 inDataFormat = 1 foldPreBnConv2D = 0 0 rawDataInElementType = 1 3 inElementType = 1 3 inWidth = 24 2 inHeight = 18 32768 inNumChannels = 64 1 numBatches = 1 1 numFrames = 1 1 inQuantFactor = 16.0 16384.0 inData = "import_config.txt0014_0001_0001_00001_00001_00002x32768.y" inFileFormat = 1 inDataNamesList = "/bev_encoder/Reshape_15_output_0, /bev_encoder/Unsqueeze_5_output_0" outDataNamesList = "/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0" outputFeature16bitNamesList = "/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0" params16bitNamesList = "/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0" perfSimConfig = /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/device_config.cfg perfSimTool = /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/ti_cnnperfsim.out tidlStatsTool = "/home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/PC_dsp_test_dl_algo.out" debugTraceLevel = 3 writeTraceLevel = 0 writeOutput = 2 postProcType = 0 compileConstraintsFlag = 83886080
tidlStatsTool = "/home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/PC_dsp_test_dl_algo.out"
This tool is required to collect the actual range of inputs. Your error log maybe result from data out of range as you passed the range collection.
inData = "import_config.txt0014_0001_0001_00001_00001_00002x32768.y"
inFileFormat = 1
inFileFormat = 2 only accept inputs as images when import tool calls tidlStatsTool. When you have multiple inputs, you can combine all tensor into one file.
Regards,
Adam
Here upload the bin files I generated.
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/tidl_5F00_io_5F00_1.bin
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/tidl_5F00_net.bin
Regards,
Adam
Hi,
We use the model exported by model_import.out in the edgeai, and it crashes when RT is running, and the log is as follows:
[C7x_1 ] 5140.784916 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle 50 [C7x_1 ] 5140.784962 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.785002 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.785040 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.785078 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.785116 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.785153 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.785191 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1 [C7x_1 ] 5140.794882 s: A0 =0x988 A1 =0x1 [C7x_1 ] 5140.794900 s: A2 =0x1 A3 =0x1 [C7x_1 ] 5140.794910 s: A4 =0x68093f40 A5 =0x1 [C7x_1 ] 5140.794920 s: A6 =0xd60 A7 =0x6486a980 [C7x_1 ] 5140.794931 s: A8 =0xb3109f90 A9 =0xb3109f94 [C7x_1 ] 5140.794942 s: A10=0x18002100 A11=0x64800080 [C7x_1 ] 5140.794953 s: A12=0x20 A13=0x6486a980 [C7x_1 ] 5140.794963 s: A14=0x0 A15=0x0 [C7x_1 ] 5140.794973 s: D0 =0x68093f40 D1 =0x8c0 [C7x_1 ] 5140.794983 s: D2 =0x0 D3 =0xb310a6b0 [C7x_1 ] 5140.794993 s: D4 =0x68094800 D5 =0x18000150 [C7x_1 ] 5140.795004 s: D6 =0x18001fc0 D7 =0x18001e80 [C7x_1 ] 5140.795015 s: D8 =0x68094800 D9 =0x0 [C7x_1 ] 5140.795026 s: D10=0x0 D11=0x90000000 [C7x_1 ] 5140.795036 s: D12=0x68000000 D13=0x68094800 [C7x_1 ] 5140.795047 s: D14=0x6486a980 D15=0xb3109db8 [C7x_1 ] 5140.795058 s: AM0=0x6b AM1=0x940 [C7x_1 ] 5140.795067 s: AM2=0x0 AM3=0x1 [C7x_1 ] 5140.795077 s: AM4=0x0 AM5=0xe8cc1ab1 [C7x_1 ] 5140.795087 s: AM6=0x5816411c AM7=0x0 [C7x_1 ] 5140.795098 s: AL0=0x460 AL1=0x1 [C7x_1 ] 5140.795107 s: AL2=0x1 AL3=0x1 [C7x_1 ] 5140.795117 s: AL4=0x8094800 AL5=0x10094800 [C7x_1 ] 5140.795128 s: AL6=0x18094800 AL7=0x7ffffff [C7x_1 ] 5140.795153 s: P0=0xfffff P1=0xfffff [C7x_1 ] 5140.795163 s: P2=0x0 P3=0x0 [C7x_1 ] 5140.795172 s: P4=0x0 P5=0xffffffff [C7x_1 ] 5140.795182 s: P6=0xffffffff P7=0xffffffff [C7x_1 ] 5140.795192 s: FPCR=0x10 FSR=0x10101012 [C7x_1 ] 5140.795203 s: GFPGFR=0x700001d GPLY=0x0 [C7x_1 ] 5140.795214 s: [C7x_1 ] =0xb333fa40 [0] [C7x_1 ] 5140.795224 s: [C7x_1 ] =0xb333fa40 [0] [C7x_1 ] 5140.795233 s: 0x4e34020b [1] [C7x_1 ] 5140.795243 s: 0x4bd0362c [2] [C7x_1 ] 5140.795252 s: 0xcdfb7be0 [3] [C7x_1 ] 5140.795261 s: 0x4dc42018 [4] [C7x_1 ] 5140.795270 s: 0xcefdbe7f [5] [C7x_1 ] 5140.795279 s: 0xce7eabf0 [6] [C7x_1 ] 5140.795289 s: 0x4dc00098 [7] [C7x_1 ] 5140.795298 s: 0x0 [1] [C7x_1 ] 5140.795306 s: 0x0 [2] [C7x_1 ] 5140.795315 s: 0x40 [3] [C7x_1 ] 5140.795324 s: 0x40 [4] [C7x_1 ] 5140.795333 s: 0x0 [5] [C7x_1 ] 5140.795341 s: 0x0 [6] [C7x_1 ] 5140.795350 s: 0x1004000 [7] [C7x_1 ] 5140.795359 s: [C7x_1 ] =0xb333f9c0 [0] [C7x_1 ] 5140.795369 s: [C7x_1 ] =0xb333f9c0 [0] [C7x_1 ] 5140.795378 s: 0x24 [1] [C7x_1 ] 5140.795387 s: 0x1 [2] [C7x_1 ] 5140.795395 s: 0x460 [3] [C7x_1 ] 5140.795405 s: 0xe0 [4] [C7x_1 ] 5140.795413 s: 0x20 [5] [C7x_1 ] 5140.795422 s: 0x0 [6] [C7x_1 ] 5140.795430 s: 0x4405000 [7] [C7x_1 ] 5140.795440 s: 0x2 [1] [C7x_1 ] 5140.795448 s: 0x8000 [2] [C7x_1 ] 5140.795457 s: 0x40 [3] [C7x_1 ] 5140.795466 s: 0x40 [4] [C7x_1 ] 5140.795475 s: 0x40 [5] [C7x_1 ] 5140.795483 s: 0x0 [6] [C7x_1 ] 5140.795492 s: 0x4006000 [7] [C7x_1 ] 5140.795501 s: [C7x_1 ] =0xb333f940 [0] [C7x_1 ] 5140.795511 s: [C7x_1 ] =0xb333f940 [0] [C7x_1 ] 5140.795520 s: 0x12 [1] [C7x_1 ] 5140.795529 s: 0x12 [2] [C7x_1 ] 5140.795538 s: 0x12 [3] [C7x_1 ] 5140.795547 s: 0x12 [4] [C7x_1 ] 5140.795555 s: 0x12 [5] [C7x_1 ] 5140.795564 s: 0x12 [6] [C7x_1 ] 5140.795573 s: 0x12 [7] [C7x_1 ] 5140.795582 s: 0x18 [1] [C7x_1 ] 5140.795590 s: 0x18 [2] [C7x_1 ] 5140.795599 s: 0x18 [3] [C7x_1 ] 5140.795608 s: 0x18 [4] [C7x_1 ] 5140.795617 s: 0x18 [5] [C7x_1 ] 5140.795625 s: 0x18 [6] [C7x_1 ] 5140.795634 s: 0x18 [7] [C7x_1 ] 5140.795643 s: [C7x_1 ] =0xb333f8c0 [0] [C7x_1 ] 5140.795652 s: [C7x_1 ] =0xb333f8c0 [0] [C7x_1 ] 5140.795662 s: 0x2901a04 [1] [C7x_1 ] 5140.795671 s: 0x4960a110 [2] [C7x_1 ] 5140.795681 s: 0x62c88106 [3] [C7x_1 ] 5140.795690 s: 0x70482848 [4] [C7x_1 ] 5140.795699 s: 0x26154f00 [5] [C7x_1 ] 5140.795708 s: 0x40c04218 [6] [C7x_1 ] 5140.795718 s: 0x61a109a [7] [C7x_1 ] 5140.795727 s: 0x7fffffff [1] [C7x_1 ] 5140.795736 s: 0x7fffffff [2] [C7x_1 ] 5140.795745 s: 0x7fffffff [3] [C7x_1 ] 5140.795755 s: 0x7fffffff [4] [C7x_1 ] 5140.795764 s: 0x7fffffff [5] [C7x_1 ] 5140.795774 s: 0x7fffffff [6] [C7x_1 ] 5140.795783 s: 0x7fffffff [7] [C7x_1 ] 5140.795792 s: [C7x_1 ] VBL0=0xb333f840 [0] [C7x_1 ] 5140.795802 s: [C7x_1 ] VBL1=0xb333f840 [0] [C7x_1 ] 5140.795812 s: 0x0 [1] [C7x_1 ] 5140.795820 s: 0x0 [2] [C7x_1 ] 5140.795829 s: 0x0 [3] [C7x_1 ] 5140.795837 s: 0x0 [4] [C7x_1 ] 5140.795845 s: 0x0 [5] [C7x_1 ] 5140.795854 s: 0x0 [6] [C7x_1 ] 5140.795862 s: 0x0 [7] [C7x_1 ] 5140.795871 s: 0x0 [1] [C7x_1 ] 5140.795879 s: 0x0 [2] [C7x_1 ] 5140.795888 s: 0x0 [3] [C7x_1 ] 5140.795896 s: 0x0 [4] [C7x_1 ] 5140.795905 s: 0x0 [5] [C7x_1 ] 5140.795913 s: 0x0 [6] [C7x_1 ] 5140.795921 s: 0x0 [7] [C7x_1 ] 5140.795930 s: [C7x_1 ] VBL2=0xb333f7c0 [0] [C7x_1 ] 5140.795940 s: [C7x_1 ] VBL3=0xb333f7c0 [0] [C7x_1 ] 5140.795949 s: 0x0 [1] [C7x_1 ] 5140.795958 s: 0x0 [2] [C7x_1 ] 5140.795967 s: 0x0 [3] [C7x_1 ] 5140.795975 s: 0x0 [4] [C7x_1 ] 5140.795984 s: 0x0 [5] [C7x_1 ] 5140.795992 s: 0x0 [6] [C7x_1 ] 5140.796000 s: 0x0 [7] [C7x_1 ] 5140.796009 s: 0x0 [1] [C7x_1 ] 5140.796017 s: 0x0 [2] [C7x_1 ] 5140.796026 s: 0x0 [3] [C7x_1 ] 5140.796034 s: 0x0 [4] [C7x_1 ] 5140.796043 s: 0x0 [5] [C7x_1 ] 5140.796051 s: 0x0 [6] [C7x_1 ] 5140.796059 s: 0x0 [7] [C7x_1 ] 5140.796068 s: [C7x_1 ] =0xb333f740 [0] [C7x_1 ] 5140.796078 s: [C7x_1 ] =0xb333f740 [0] [C7x_1 ] 5140.796087 s: 0x4000 [1] [C7x_1 ] 5140.796096 s: 0x4000 [2] [C7x_1 ] 5140.796104 s: 0x4000 [3] [C7x_1 ] 5140.796113 s: 0x4000 [4] [C7x_1 ] 5140.796122 s: 0x4000 [5] [C7x_1 ] 5140.796130 s: 0x4000 [6] [C7x_1 ] 5140.796139 s: 0x4000 [7] [C7x_1 ] 5140.796148 s: 0x0 [1] [C7x_1 ] 5140.796156 s: 0x0 [2] [C7x_1 ] 5140.796165 s: 0x0 [3] [C7x_1 ] 5140.796174 s: 0x0 [4] [C7x_1 ] 5140.796182 s: 0x0 [5] [C7x_1 ] 5140.796191 s: 0x0 [6] [C7x_1 ] 5140.796199 s: 0x0 [7] [C7x_1 ] 5140.796207 s: [C7x_1 ] =0xb333f6c0 [0] [C7x_1 ] 5140.796217 s: [C7x_1 ] VBL7=0xb333f6c0 [0] [C7x_1 ] 5140.796226 s: 0x4 [1] [C7x_1 ] 5140.796235 s: 0x4 [2] [C7x_1 ] 5140.796244 s: 0x4 [3] [C7x_1 ] 5140.796253 s: 0x4 [4] [C7x_1 ] 5140.796261 s: 0x4 [5] [C7x_1 ] 5140.796269 s: 0x4 [6] [C7x_1 ] 5140.796278 s: 0x4 [7] [C7x_1 ] 5140.796287 s: 0x7ff0 [1] [C7x_1 ] 5140.796296 s: 0x7ff0 [2] [C7x_1 ] 5140.796304 s: 0x7ff0 [3] [C7x_1 ] 5140.796313 s: 0x7ff0 [4] [C7x_1 ] 5140.796322 s: 0x7ff0 [5] [C7x_1 ] 5140.796331 s: 0x7ff0 [6] [C7x_1 ] 5140.796340 s: 0x7ff0 [7] [C7x_1 ] 5140.796348 s: [C7x_1 ] VB0=0xb333fe40 [0] [C7x_1 ] 5140.796358 s: [C7x_1 ] VB1=0xb333fe40 [0] [C7x_1 ] 5140.796368 s: 0x0 [1] [C7x_1 ] 5140.796376 s: 0x0 [2] [C7x_1 ] 5140.796385 s: 0x0 [3] [C7x_1 ] 5140.796393 s: 0x0 [4] [C7x_1 ] 5140.796402 s: 0x0 [5] [C7x_1 ] 5140.796410 s: 0x0 [6] [C7x_1 ] 5140.796419 s: 0x0 [7] [C7x_1 ] 5140.796427 s: 0x0 [1] [C7x_1 ] 5140.796436 s: 0x0 [2] [C7x_1 ] 5140.796444 s: 0x0 [3] [C7x_1 ] 5140.796452 s: 0x0 [4] [C7x_1 ] 5140.796461 s: 0x0 [5] [C7x_1 ] 5140.796469 s: 0x0 [6] [C7x_1 ] 5140.796478 s: 0x0 [7] [C7x_1 ] 5140.796486 s: [C7x_1 ] VB2=0xb333fdc0 [0] [C7x_1 ] 5140.796496 s: [C7x_1 ] =0xb333fdc0 [0] [C7x_1 ] 5140.796505 s: 0x0 [1] [C7x_1 ] 5140.796514 s: 0x1 [2] [C7x_1 ] 5140.796522 s: 0x0 [3] [C7x_1 ] 5140.796531 s: 0x0 [4] [C7x_1 ] 5140.796539 s: 0x0 [5] [C7x_1 ] 5140.796548 s: 0x0 [6] [C7x_1 ] 5140.796556 s: 0x0 [7] [C7x_1 ] 5140.796565 s: 0x24 [1] [C7x_1 ] 5140.796574 s: 0x1 [2] [C7x_1 ] 5140.796582 s: 0x480 [3] [C7x_1 ] 5140.796591 s: 0x4a0 [4] [C7x_1 ] 5140.796600 s: 0x0 [5] [C7x_1 ] 5140.796609 s: 0x0 [6] [C7x_1 ] 5140.796617 s: 0x5005001 [7] [C7x_1 ] 5140.796627 s: [C7x_1 ] VB4=0xb333fd40 [0] [C7x_1 ] 5140.801703 s: 0x0 [7] [C7x_1 ] 5140.801711 s: [C7x_1 ] =0xb333f180 [0] [C7x_1 ] 5140.801721 s: [C7x_1 ] =0xb333f180 [0] [C7x_1 ] 5140.801730 s: 0x24 [1] [C7x_1 ] 5140.801739 s: 0x1 [2] [C7x_1 ] 5140.801747 s: 0x480 [3] [C7x_1 ] 5140.801756 s: 0x4a0 [4] [C7x_1 ] 5140.801765 s: 0x0 [5] [C7x_1 ] 5140.801773 s: 0x0 [6] [C7x_1 ] 5140.801781 s: 0x5005001 [7] [C7x_1 ] 5140.801791 s: 0x5 [1] [C7x_1 ] 5140.801799 s: 0x1 [2] [C7x_1 ] 5140.801808 s: 0xa0 [3] [C7x_1 ] 5140.801816 s: 0x0 [4] [C7x_1 ] 5140.801825 s: 0x0 [5] [C7x_1 ] 5140.801833 s: 0x0 [6] [C7x_1 ] 5140.801842 s: 0x64845980 [7] [C7x_1 ] 5140.801851 s: [C7x_1 ] =0xb333f200 [0] [C7x_1 ] 5140.801860 s: [C7x_1 ] =0xb333f200 [0] [C7x_1 ] 5140.801870 s: 0x64853600 [1] [C7x_1 ] 5140.801879 s: 0x64846140 [2] [C7x_1 ] 5140.801888 s: 0x64845980 [3] [C7x_1 ] 5140.801897 s: 0x64845980 [4] [C7x_1 ] 5140.801907 s: 0x64845980 [5] [C7x_1 ] 5140.801916 s: 0x0 [6] [C7x_1 ] 5140.801924 s: 0x0 [7] [C7x_1 ] 5140.801933 s: 0x50000 [1] [C7x_1 ] 5140.801942 s: 0x14c0000 [2] [C7x_1 ] 5140.801951 s: 0x29b00000 [3] [C7x_1 ] 5140.801960 s: 0x0 [4] [C7x_1 ] 5140.801969 s: 0x0 [5] [C7x_1 ] 5140.801977 s: 0x49f0 [6] [C7x_1 ] 5140.801987 s: 0x0 [7] [C7x_1 ] 5140.801995 s: [C7x_1 ] =0xb333f280 [0] [C7x_1 ] 5140.802004 s: [C7x_1 ] =0xb333f280 [0] [C7x_1 ] 5140.802014 s: 0x3 [1] [C7x_1 ] 5140.802022 s: 0x3 [2] [C7x_1 ] 5140.802031 s: 0x161 [3] [C7x_1 ] 5140.802040 s: 0x1 [4] [C7x_1 ] 5140.802049 s: 0x7c0 [5] [C7x_1 ] 5140.802057 s: 0x0 [6] [C7x_1 ] 5140.802066 s: 0xd005001 [7] [C7x_1 ] 5140.802075 s: 0x2 [1] [C7x_1 ] 5140.802084 s: 0x3 [2] [C7x_1 ] 5140.802092 s: 0xe1 [3] [C7x_1 ] 5140.802101 s: 0x0 [4] [C7x_1 ] 5140.802110 s: 0x0 [5] [C7x_1 ] 5140.802118 s: 0x0 [6] [C7x_1 ] 5140.802127 s: 0x647fff7e [7] [C7x_1 ] 5140.802136 s: [C7x_1 ] =0xb333f300 [0] [C7x_1 ] 5140.802145 s: [C7x_1 ] =0xb333f300 [0] [C7x_1 ] 5140.802154 s: 0x6487067e [1] [C7x_1 ] 5140.802164 s: 0x6487067e [2] [C7x_1 ] 5140.802173 s: 0x6487057e [3] [C7x_1 ] 5140.802182 s: 0x647fff7e [4] [C7x_1 ] 5140.802191 s: 0x647fff7e [5] [C7x_1 ] 5140.802201 s: 0x0 [6] [C7x_1 ] 5140.802209 s: 0x0 [7] [C7x_1 ] 5140.802218 s: 0x70800 [1] [C7x_1 ] 5140.802227 s: 0x0 [2] [C7x_1 ] 5140.802236 s: 0x3833f000 [3] [C7x_1 ] 5140.802245 s: 0x40 [4] [C7x_1 ] 5140.802253 s: 0x80000000 [5] [C7x_1 ] 5140.802263 s: 0x40 [6] [C7x_1 ] 5140.802271 s: 0x0 [7] [C7x_1 ] 5140.802280 s: [C7x_1 ] =0xb333f440 [0] [C7x_1 ] 5140.802290 s: [C7x_1 ] =0xb333f440 [0] [C7x_1 ] 5140.802299 s: 0x0 [1] [C7x_1 ] 5140.802308 s: 0x0 [2] [C7x_1 ] 5140.802316 s: 0x40 [3] [C7x_1 ] 5140.802325 s: 0x40 [4] [C7x_1 ] 5140.802334 s: 0x0 [5] [C7x_1 ] 5140.802343 s: 0x0 [6] [C7x_1 ] 5140.802351 s: 0x1004000 [7] [C7x_1 ] 5140.802360 s: 0x0 [1] [C7x_1 ] 5140.802369 s: 0x0 [2] [C7x_1 ] 5140.802378 s: 0x40 [3] [C7x_1 ] 5140.802386 s: 0x40 [4] [C7x_1 ] 5140.802395 s: 0x0 [5] [C7x_1 ] 5140.802403 s: 0x0 [6] [C7x_1 ] 5140.802412 s: 0x1004000 [7] [C7x_1 ] 5140.802421 s: [C7x_1 ] =0xb333f3c0 [0] [C7x_1 ] 5140.802430 s: [C7x_1 ] SA3CR=0xb333f3c0 [0] [C7x_1 ] 5140.802440 s: 0x24 [1] [C7x_1 ] 5140.802449 s: 0x1 [2] [C7x_1 ] 5140.802457 s: 0x460 [3] [C7x_1 ] 5140.802466 s: 0xe0 [4] [C7x_1 ] 5140.802475 s: 0x20 [5] [C7x_1 ] 5140.802483 s: 0x0 [6] [C7x_1 ] 5140.802492 s: 0x4405000 [7] [C7x_1 ] 5140.802501 s: 0x0 [1] [C7x_1 ] 5140.802510 s: 0x0 [2] [C7x_1 ] 5140.802518 s: 0x0 [3] [C7x_1 ] 5140.802527 s: 0x0 [4] [C7x_1 ] 5140.802535 s: 0x0 [5] [C7x_1 ] 5140.802544 s: 0x0 [6] [C7x_1 ] 5140.802552 s: 0x0 [7] [C7x_1 ] 5140.802561 s: [C7x_1 ] SA0CNTR0=0xb333f540 [0] [C7x_1 ] 5140.802570 s: [C7x_1 ] SA1CNTR0=0xb333f540 [0] [C7x_1 ] 5140.802581 s: 0x0 [1] [C7x_1 ] 5140.802589 s: 0x0 [2] [C7x_1 ] 5140.802598 s: 0x0 [3] [C7x_1 ] 5140.802606 s: 0x0 [4] [C7x_1 ] 5140.802615 s: 0x0 [5] [C7x_1 ] 5140.802623 s: 0x0 [6] [C7x_1 ] 5140.802632 s: 0x0 [7] [C7x_1 ] 5140.802640 s: 0x0 [1] [C7x_1 ] 5140.802649 s: 0x0 [2] [C7x_1 ] 5140.802657 s: 0x0 [3] [C7x_1 ] 5140.802666 s: 0x0 [4] [C7x_1 ] 5140.802674 s: 0x0 [5] [C7x_1 ] 5140.802682 s: 0x0 [6] [C7x_1 ] 5140.802691 s: 0x0 [7] [C7x_1 ] 5140.802699 s: [C7x_1 ] =0xb333f4c0 [0] [C7x_1 ] 5140.802709 s: [C7x_1 ] SA3CNTR0=0xb333f4c0 [0] [C7x_1 ] 5140.802719 s: 0x3c0 [1] [C7x_1 ] 5140.802728 s: 0x0 [2] [C7x_1 ] 5140.802736 s: 0x460 [3] [C7x_1 ] 5140.802745 s: 0x20 [4] [C7x_1 ] 5140.802754 s: 0x6 [5] [C7x_1 ] 5140.802763 s: 0x1 [6] [C7x_1 ] 5140.802771 s: 0xa0 [7] [C7x_1 ] 5140.802780 s: 0x0 [1] [C7x_1 ] 5140.802789 s: 0x0 [2] [C7x_1 ] 5140.802797 s: 0x0 [3] [C7x_1 ] 5140.802806 s: 0x0 [4] [C7x_1 ] 5140.802814 s: 0x0 [5] [C7x_1 ] 5140.802822 s: 0x0 [6] [C7x_1 ] 5140.802831 s: 0x0 [7]
Could you help us confirm if there is an existing bug?
Regards,
hongyao
Hi hongyao,
I am able to reproduce your issue with the log on evm:
root@j784s4-evm:/opt/0711_simple_demo2# /opt/tidl_test/TI_DEVICE_armv8_test_dl_algo_host_rt.out s:tidl_infer.txt
Processing config file #0 : tidl_infer.txt
Input : dataId=0, name=/bev_encoder/Reshape_15_output_0, elementType 1, scale=16.000000, zero point=0, layout=0
Input : dataId=1, name=/bev_encoder/Unsqueeze_5_output_0, elementType 3, scale=16384.000000, zero point=0, layout=0
Ouput : dataId=6, name=/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0, elementType 3, scale=1024.000000, zero point
1914140, 1.825 0xffff7486d010
worstCaseDelay for Pre-emption is 10.9883108
Network File Read done
APP: Init ... !!!
63.817272 s: MEM: Init ... !!!
63.817316 s: MEM: Initialized DMA HEAP (fd=5) !!!
63.817473 s: MEM: Init ... Done !!!
63.817490 s: IPC: Init ... !!!
63.852695 s: IPC: Init ... Done !!!
REMOTE_SERVICE: Init ... !!!
REMOTE_SERVICE: Init ... Done !!!
63.867107 s: GTC Frequency = 200 MHz
APP: Init ... Done !!!
63.868923 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
63.868935 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
63.868943 s: VX_ZONE_INFO: Globally Enabled VX_ZONE_INFO
63.870965 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-0
63.871070 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-1
63.871155 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-2
63.871252 s: VX_ZONE_INFO: [tivxPlatformCreateTargetId:169] Added target MPU-3
63.871263 s: VX_ZONE_INFO: [tivxInitLocal:202] Initialization Done !!!
63.871273 s: VX_ZONE_INFO: Globally Disabled VX_ZONE_INFO
[C7x_1 ] 63.885981 s: TIDL_initDebugTraceParams Done
[C7x_1 ] 63.886073 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 63.886101 s: ===================================================
[C7x_1 ] 63.886138 s: Link Id 1610612800, Number of TR required = 1
[C7x_1 ] 63.886166 s: ===================================================
[C7x_1 ] 63.886196 s: Link Id 1694498880, Number of TR required = 1
[C7x_1 ] 63.886223 s: ===================================================
[C7x_1 ] 63.886260 s: Link Id 2684354656, Number of TR required = 3
[C7x_1 ] 63.886288 s: ===================================================
[C7x_1 ] 63.886317 s: Link Id 2717909088, Number of TR required = 1
[C7x_1 ] 63.886345 s: ===================================================
[C7x_1 ] 63.886373 s: Link Id 2734686304, Number of TR required = 1
[C7x_1 ] 63.886400 s: ===================================================
[C7x_1 ] 63.886428 s: Link Id 2751463520, Number of TR required = 1
[C7x_1 ] 63.886456 s: ===================================================
[C7x_1 ] 63.886484 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 63.886511 s: ===================================================
[C7x_1 ] 63.888033 s: PREEMPTION: Requesting memory of size 3014656 for targetPriority = 256
[C7x_1 ] 63.888054 s:
[C7x_1 ] 63.888072 s: --------------------------------------------
[C7x_1 ] 63.888098 s: TIDL Memory size requiement (record wise):
[C7x_1 ] 63.888139 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
[C7x_1 ] 63.888184 s: 0 , DDR Non-cacheable , Persistent , 128, 19.67 , 0x00000000
[C7x_1 ] 63.888227 s: 1 , DDR Cacheable , Persistent , 128, 0.66 , 0x00000000
[C7x_1 ] 63.888267 s: 2 , L1D , Scratch , 128, 16.00 , 0x00000000
[C7x_1 ] 63.888309 s: 3 , L2 , Scratch , 128, 448.00 , 0x00000000
[C7x_1 ] 63.888349 s: 4 , L3/MSMC , Scratch , 128, 2944.00 , 0x00000000
[C7x_1 ] 63.888391 s: 5 , DDR Cacheable , Persistent , 128, 352.31 , 0x00000000
[C7x_1 ] 63.888431 s: 6 , DDR Non-cacheable , Scratch , 128, 0.88 , 0x00000000
[C7x_1 ] 63.888472 s: 7 , DDR Non-cacheable , Persistent , 128, 10607.25, 0x00000000
[C7x_1 ] 63.888512 s: 8 , DDR Non-cacheable , Scratch , 128, 0.13 , 0x00000000
[C7x_1 ] 63.888553 s: 9 , DDR Non-cacheable , Scratch , 128, 3.13 , 0x00000000
[C7x_1 ] 63.888594 s: 10 , DDR Cacheable , Persistent , 128, 293.47 , 0x00000000
[C7x_1 ] 63.888635 s: 11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x00000000
[C7x_1 ] 63.888676 s: 12 , DDR Non-cacheable , Persistent , 128, 2944.00 , 0x00000000
[C7x_1 ] 63.888717 s: 13 , DDR Cacheable , Persistent , 128, 1292.90 , 0x00000000
[C7x_1 ] 63.888757 s: 14 , DDR Non-cacheable , Persistent , 128, 0.00 , 0x00000000
[C7x_1 ] 63.888799 s: 15 , DDR Cacheable , Persistent , 128, 578.25 , 0x00000000
[C7x_1 ] 63.888828 s: --------------------------------------------
[C7x_1 ] 63.888853 s: Total memory size requirement (space wise):
[C7x_1 ] 63.888873 s: Mem Space , Size(KBytes)
[C7x_1 ] 63.888891 s: L1D , 16.00
[C7x_1 ] 63.888907 s: L2 , 448.00
[C7x_1 ] 63.888924 s: L3/MSMC , 2944.00
[C7x_1 ] 63.888943 s: DDR Cacheable, 6613.84
RT-Profile: TIDLRT_init_profiling
[C7x_1 ] 63.888962 s: DDR Non-cacheable, 13575.05
tidlrt_create : 99019745 ns,
[C7x_1 ] 63.888985 s: --------------------------------------------
tidl_rt_ovx_Init : 58352615 ns,
vxCreateContext : 3640540 ns,
init_tidl_tiovx : 3727770 ns,
create_graph_tidl_tiovx : 2426425 ns,
[C7x_1 ] 63.889021 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
verify_graph_tidl_tiovx : 30447730 ns,
tivxTIDLLoadKernels : 14305 ns,
mapConfig : 1032760 ns,
tivxAddKernelTIDL : 64830 ns,
[C7x_1 ] 63.889060 s: To get the actual TIDL memory requirement make sure to run on EVM with
mapNetwork : 2122345 ns,
setCreateParams : 199740 ns,
[C7x_1 ] 63.889083 s: debugTraceLevel = 2
setArgs : 290650 ns,
[C7x_1 ] 63.889093 s:
vxCreateUserDataObject : 2641410 ns,
vxMapUserDataObject : 1391545 ns,
memcopy_network_buffer : 696710 ns,
[C7x_1 ] 63.889113 s: --------------------------------------------
vxUnmapUserDataObject : 3655 ns,
[C7x_1 ] 63.889189 s: TIDL init call from ivision API
# NETWORK_INIT_TIME = 416.69 (in ms, c7x @1GHz)
[C7x_1 ] 63.889205 s:
[C7x_1 ] 63.889223 s: --------------------------------------------
[C7x_1 ] 63.889247 s: TIDL Memory size requiement (record wise):
[C7x_1 ] 63.889287 s: MemRecNum , Space , Attribute , Alignment , Size(KBytes), BasePtr
[C7x_1 ] 63.889329 s: 0 , DDR Non-cacheable , Persistent , 128, 19.67 , 0x00000000
[C7x_1 ] 63.889371 s: 1 , DDR Cacheable , Persistent , 128, 0.66 , 0x0806c400
[C7x_1 ] 63.889412 s: 2 , L1D , Scratch , 128, 16.00 , 0x64e00000
Freeing memory for user provided Net
[C7x_1 ] 63.889453 s: 3 , L2 , Scratch , 128, 448.00 , 0x64800000
[C7x_1 ] 63.889494 s: 4 , L3/MSMC , Scratch , 128, 2944.00 , 0x68000000
[C7x_1 ] 63.889535 s: 5 , DDR Cacheable , Persistent , 128, 352.31 , 0x0806c800
[C7x_1 ] 63.889576 s: 6 , DDR Non-cacheable , Scratch , 128, 0.88 , 0x10000000
[C7x_1 ] 63.889617 s: 7 , DDR Non-cacheable , Persistent , 128, 10607.25, 0x00005000
[C7x_1 ] 63.889657 s: 8 , DDR Non-cacheable , Scratch , 128, 0.13 , 0x10000400
[C7x_1 ] 63.889698 s: 9 , DDR Non-cacheable , Scratch , 128, 3.13 , 0x10000800
[C7x_1 ] 63.889739 s: 10 , DDR Cacheable , Persistent , 128, 293.47 , 0x080c4b00
[C7x_1 ] 63.889779 s: 11 , DDR Cacheable , Scratch , 128, 4096.25 , 0x18000000
[C7x_1 ] 63.889820 s: 12 , DDR Non-cacheable , Persistent , 128, 2944.00 , 0x00a61000
[C7x_1 ] 63.889861 s: 13 , DDR Cacheable , Persistent , 128, 1292.90 , 0x0810e200
[C7x_1 ] 63.889902 s: 14 , DDR Non-cacheable , Persistent , 128, 0.00 , 0x00d41000
[C7x_1 ] 63.889943 s: 15 , DDR Cacheable , Persistent , 128, 578.25 , 0x08251700
[C7x_1 ] 63.889971 s: --------------------------------------------
[C7x_1 ] 63.889996 s: Total memory size requirement (space wise):
[C7x_1 ] 63.890016 s: Mem Space , Size(KBytes)
[C7x_1 ] 63.890033 s: L1D , 16.00
[C7x_1 ] 63.890050 s: L2 , 448.00
[C7x_1 ] 63.890067 s: L3/MSMC , 2944.00
[C7x_1 ] 63.890085 s: DDR Cacheable, 6613.84
[C7x_1 ] 63.890104 s: DDR Non-cacheable, 13575.05
Instance created for tidl_infer.txt
[C7x_1 ] 63.890127 s: --------------------------------------------
[C7x_1 ] 63.890163 s: NOTE: Memory requirement in host emulation can be different from the same on EVM
[C7x_1 ] 63.890201 s: To get the actual TIDL memory requirement make sure to run on EVM with
[C7x_1 ] 63.890225 s: debugTraceLevel = 2
[C7x_1 ] 63.890234 s:
[C7x_1 ] 63.890254 s: --------------------------------------------
[C7x_1 ] 63.892797 s: Alg Init for Layer # - 2
[C7x_1 ] 63.892843 s: Link Id 32, Number of TR required = 1
Processing Cnt : 0, InstCnt : 0 output/tidl_net.bin!
[C7x_1 ] 63.892871 s: ===================================================
[C7x_1 ] 63.892901 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 63.892929 s: ===================================================
[C7x_1 ] 63.892959 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 63.892986 s: ===================================================
[C7x_1 ] 63.893006 s: Link Index 32
[C7x_1 ] 63.893029 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 63.893058 s: Link->src-> icnt (dim); 27648 1 (0) 1 (0) 1 (0)
[C7x_1 ] 63.893091 s: Link->sink-> icnt (dim); 27648 1 (27648) 1 (0) 1 (0)
[C7x_1 ] 63.893109 s: srcMemPtr: 0
[C7x_1 ] 63.893126 s: dstMemPtr: 1686110208
[C7x_1 ] 63.893182 s: Link Id 32, Number of TR required = 1
[C7x_1 ] 63.893210 s: ===================================================
[C7x_1 ] 63.893236 s: Alg Init for Layer # - 3
[C7x_1 ] 63.893276 s: Link Id 1073741872, Number of TR required = 1
[C7x_1 ] 63.893305 s: ===================================================
[C7x_1 ] 63.893337 s: Link Id 562950490292272, Number of TR required = 2
[C7x_1 ] 63.893365 s: ===================================================
[C7x_1 ] 63.893395 s: Link Id 1073741872, Number of TR required = 1
[C7x_1 ] 63.893422 s: ===================================================
[C7x_1 ] 63.893455 s: Link Id 562950490292272, Number of TR required = 2
[C7x_1 ] 63.893483 s: ===================================================
[C7x_1 ] 63.893514 s: Link Id 1073741872, Number of TR required = 1
[C7x_1 ] 63.893542 s: ===================================================
[C7x_1 ] 63.893563 s: Link Index 1073741872
[C7x_1 ] 63.893586 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 63.893617 s: Link->src-> icnt (dim); 1536 18 (1536) 1 (27648) 1 (0)
[C7x_1 ] 63.893651 s: Link->sink-> icnt (dim); 1536 18 (1536) 1 (27648) 1 (0)
[C7x_1 ] 63.893673 s: srcMemPtr: 1746927616
[C7x_1 ] 63.893691 s: dstMemPtr: 1686110208
[C7x_1 ] 63.893723 s: Link Id 562950490292272, Number of TR required = 2
[C7x_1 ] 63.893752 s: ===================================================
[C7x_1 ] 63.893776 s: Link Index 562950490292272
[C7x_1 ] 63.893799 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 63.893832 s: Link->src-> icnt (dim); 32768 2 (32768) 1 (65536) 1 (0)
[C7x_1 ] 63.893866 s: Link->sink-> icnt (dim); 32768 2 (32768) 1 (65536) 1 (0)
[C7x_1 ] 63.893885 s: srcMemPtr: 0
[C7x_1 ] 63.893901 s: dstMemPtr: 1686165504
[C7x_1 ] 63.893972 s: Link Id 1073741872, Number of TR required = 1
[C7x_1 ] 63.894000 s: ===================================================
[C7x_1 ] 63.894033 s: Link Id 562950490292272, Number of TR required = 2
[C7x_1 ] 63.894062 s: ===================================================
[C7x_1 ] 63.894086 s: Alg Init for Layer # - 4
[C7x_1 ] 63.894125 s: Link Id 1610612800, Number of TR required = 1
[C7x_1 ] 63.894153 s: ===================================================
[C7x_1 ] 63.894183 s: Link Id 1694498880, Number of TR required = 1
Warning :: File read for binary data load is not suffcient in size to fill the input tensor, Filling it with zero
[C7x_1 ] 63.894210 s: ===================================================
[C7x_1 ] 63.894239 s: Link Id 1610612800, Number of TR required = 1
[C7x_1 ] 63.894267 s: ===================================================
[C7x_1 ] 63.894296 s: Link Id 1694498880, Number of TR required = 1
[C7x_1 ] 63.894323 s: ===================================================
[C7x_1 ] 63.894354 s: Link Id 1610612800, Number of TR required = 1
[C7x_1 ] 63.894381 s: ===================================================
[C7x_1 ] 63.894402 s: Link Index 1610612800
[C7x_1 ] 63.894425 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 63.894457 s: Link->src-> icnt (dim); 64 2048 (64) 16 (131072) 1 (0)
[C7x_1 ] 63.894490 s: Link->sink-> icnt (dim); 64 2048 (64) 2 (131072) 8 (0)
[C7x_1 ] 63.894512 s: srcMemPtr: 1744830464
[C7x_1 ] 63.894530 s: dstMemPtr: 1686110208
[C7x_1 ] 63.894560 s: Link Id 1694498880, Number of TR required = 1
[C7x_1 ] 63.894588 s: ===================================================
[C7x_1 ] 63.894609 s: Link Index 1694498880
[C7x_1 ] 63.894632 s: Flow 1 Src Shape: 2 Sink Shape 0
[C7x_1 ] 63.894664 s: Link->src-> icnt (dim); 2048 64 (2048) 2 (131072) 8 (0)
[C7x_1 ] 63.894698 s: Link->sink-> icnt (dim); 2048 64 (32768) 16 (2048) 1 (0)
[C7x_1 ] 63.894720 s: srcMemPtr: 1746927616
[C7x_1 ] 63.894738 s: dstMemPtr: 4295148544
[C7x_1 ] 63.894797 s: Link Id 1610612800, Number of TR required = 1
[C7x_1 ] 63.894826 s: ===================================================
[C7x_1 ] 63.894855 s: Link Id 1694498880, Number of TR required = 1
[C7x_1 ] 63.894882 s: ===================================================
[C7x_1 ] 63.894906 s: Alg Init for Layer # - 5
[C7x_1 ] 63.894935 s: Alg Init for Layer # - 6
[C7x_1 ] 63.894979 s: Link Id 2684354656, Number of TR required = 3
[C7x_1 ] 63.895007 s: ===================================================
[C7x_1 ] 63.895036 s: Link Id 2717909088, Number of TR required = 1
[C7x_1 ] 63.895063 s: ===================================================
[C7x_1 ] 63.895092 s: Link Id 2734686304, Number of TR required = 1
[C7x_1 ] 63.895120 s: ===================================================
[C7x_1 ] 63.895148 s: Link Id 2751463520, Number of TR required = 1
[C7x_1 ] 63.895175 s: ===================================================
[C7x_1 ] 63.895204 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 63.895231 s: ===================================================
[C7x_1 ] 63.896802 s: Link Id 2684354656, Number of TR required = 3
[C7x_1 ] 63.896831 s: ===================================================
[C7x_1 ] 63.896861 s: Link Id 2717909088, Number of TR required = 1
[C7x_1 ] 63.896888 s: ===================================================
[C7x_1 ] 63.896917 s: Link Id 2734686304, Number of TR required = 1
Freeing memory for user provided Net
----------------------- TIDL Process with TARGET DATA FLOW ------------------------
[C7x_1 ] 63.896945 s: ===================================================
[C7x_1 ] 63.896973 s: Link Id 2751463520, Number of TR required = 1
[C7x_1 ] 63.897000 s: ===================================================
[C7x_1 ] 63.897029 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 63.897056 s: ===================================================
[C7x_1 ] 63.898561 s: Link Id 2684354656, Number of TR required = 3
[C7x_1 ] 63.898590 s: ===================================================
[C7x_1 ] 63.898619 s: Link Id 2717909088, Number of TR required = 1
[C7x_1 ] 63.898647 s: ===================================================
[C7x_1 ] 63.898676 s: Link Id 2734686304, Number of TR required = 1
[C7x_1 ] 63.898704 s: ===================================================
[C7x_1 ] 63.898732 s: Link Id 2751463520, Number of TR required = 1
[C7x_1 ] 63.898760 s: ===================================================
[C7x_1 ] 63.898788 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 63.898816 s: ===================================================
[C7x_1 ] 63.900318 s: Link Id 2684354656, Number of TR required = 3
[C7x_1 ] 63.900347 s: ===================================================
[C7x_1 ] 63.900368 s: Link Index 2684354656
[C7x_1 ] 63.900391 s: Flow 0 Src Shape: 0 Sink Shape 0
[C7x_1 ] 63.900422 s: Link->src-> icnt (dim); 450 128 (16384) 1 (450) 1 (0)
[C7x_1 ] 63.900456 s: Link->sink-> icnt (dim); 450 128 (1984) 1 (450) 1 (0)
[C7x_1 ] 63.900478 s: srcMemPtr: 4295148544
[C7x_1 ] 63.900495 s: dstMemPtr: 1686110336
[C7x_1 ] 63.900519 s: Flow 1 Src Shape: 0 Sink Shape 0
[C7x_1 ] 63.900552 s: Link->src-> icnt (dim); 192 128 (16384) 82 (192) 3 (2097152)
[C7x_1 ] 63.900586 s: Link->sink-> icnt (dim); 192 128 (1984) 169 (192) 1 (0)
[C7x_1 ] 63.900608 s: srcMemPtr: 4295148544
[C7x_1 ] 63.900625 s: dstMemPtr: 1686110336
[C7x_1 ] 63.900648 s: Flow 2 Src Shape: 0 Sink Shape 0
[C7x_1 ] 63.900679 s: Link->src-> icnt (dim); 190 128 (16384) 1 (192) 3 (0)
[C7x_1 ] 63.900710 s: Link->sink-> icnt (dim); 0 1 (0) 1 (0) 1 (0)
[C7x_1 ] 63.900730 s: srcMemPtr: 4295148994
[C7x_1 ] 63.900747 s: dstMemPtr: 1686110786
[C7x_1 ] 63.900775 s: Link Id 2717909088, Number of TR required = 1
[C7x_1 ] 63.900803 s: ===================================================
[C7x_1 ] 63.900823 s: Link Index 2717909088
[C7x_1 ] 63.900847 s: Flow 1 Src Shape: 0 Sink Shape 0
[C7x_1 ] 63.900878 s: Link->src-> icnt (dim); 1152 256 (1152) 1 (1152) 1 (0)
[C7x_1 ] 63.900913 s: Link->sink-> icnt (dim); 1152 256 (1188) 1 (1152) 1 (304128)
[C7x_1 ] 63.900936 s: srcMemPtr: 4431615744
[C7x_1 ] 63.900953 s: dstMemPtr: 1744830464
[C7x_1 ] 63.900981 s: Link Id 2734686304, Number of TR required = 1
[C7x_1 ] 63.901008 s: ===================================================
[C7x_1 ] 63.901029 s: Link Index 2734686304
[C7x_1 ] 63.901052 s: Flow 1 Src Shape: 0 Sink Shape 2
[C7x_1 ] 63.901084 s: Link->src-> icnt (dim); 1152 32 (1188) 8 (38016) 1 (0)
[C7x_1 ] 63.901118 s: Link->sink-> icnt (dim); 1152 32 (1184) 2 (37888) 4 (0)
[C7x_1 ] 63.901139 s: srcMemPtr: 1744830464
[C7x_1 ] 63.901156 s: dstMemPtr: 1686395264
[C7x_1 ] 63.901184 s: Link Id 2751463520, Number of TR required = 1
[C7x_1 ] 63.901212 s: ===================================================
[C7x_1 ] 63.901232 s: Link Index 2751463520
[C7x_1 ] 63.901255 s: Flow 1 Src Shape: 0 Sink Shape 0
[C7x_1 ] 63.901285 s: Link->src-> icnt (dim); 4 256 (4) 1 (4) 1 (1024)
[C7x_1 ] 63.901315 s: Link->sink-> icnt (dim); 4 256 (4) 1 (4) 1 (0)
[C7x_1 ] 63.901335 s: srcMemPtr: 4432205568
[C7x_1 ] 63.901353 s: dstMemPtr: 1686546816
[C7x_1 ] 63.901380 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 63.901408 s: ===================================================
[C7x_1 ] 63.901428 s: Link Index 2768240736
[C7x_1 ] 63.901451 s: Flow 1 Src Shape: 2 Sink Shape 0
[C7x_1 ] 63.901481 s: Link->src-> icnt (dim); 96 32 (224) 2 (7168) 680 (0)
[C7x_1 ] 63.901516 s: Link->sink-> icnt (dim); 96 32 (16800) 17 (537600) 84 (96)
[C7x_1 ] 63.901537 s: srcMemPtr: 1745438720
[C7x_1 ] 63.901552 s: dstMemPtr: 0
[C7x_1 ] 63.905674 s: Start Layer Idx 6
[C7x_1 ] 63.905697 s: kerInitArgs->funcStyle 1
[C7x_1 ] 63.905720 s: kerInitArgs->No 256
[C7x_1 ] 63.905743 s: kerInitArgs->inChOffset 1984
[C7x_1 ] 63.905766 s: kerInitArgs->validColsIn 450
[C7x_1 ] 63.905788 s: kerInitArgs->validColsPerRowIn 0
[C7x_1 ] 63.905810 s: kerInitArgs->validRowsIn 0
[C7x_1 ] 63.905832 s: kerInitArgs->inputPitchPerRow 256
[C7x_1 ] 63.905855 s: kerInitArgs->outputPitchPerRow 256
[C7x_1 ] 63.905877 s: kerInitArgs->inWidth 128
[C7x_1 ] 63.905899 s: kerInitArgs->pad 0
[C7x_1 ] 63.905922 s: kerInitArgs->maxHeight 128
[C7x_1 ] 63.905944 s: kerInitArgs->subMChannels 32
[C7x_1 ] 63.905966 s: kerInitArgs->Fr 3
[C7x_1 ] 63.905987 s: kerInitArgs->Fc 3
[C7x_1 ] 63.906009 s: kerInitArgs->strideX 1
[C7x_1 ] 63.906030 s: kerInitArgs->strideY 1
[C7x_1 ] 63.906052 s: kerInitArgs->dilationX 1
[C7x_1 ] 63.906073 s: kerInitArgs->dilationY 1
[C7x_1 ] 63.906096 s: kerInitArgs->bias 32512
[C7x_1 ] 63.906118 s: kerInitArgs->activationType 2
[C7x_1 ] 63.906139 s: kerInitArgs->mode 0
[C7x_1 ] 63.906161 s: src0Addr->data_type 1
[C7x_1 ] 63.906183 s: src0Addr->dim_x 1152
[C7x_1 ] 63.906206 s: src0Addr->dim_y 32
[C7x_1 ] 63.906228 s: src0Addr->stride_y 2368
[C7x_1 ] 63.906250 s: src1Addr->data_type 1
[C7x_1 ] 63.906272 s: src1Addr->dim_x 708
[C7x_1 ] 63.906295 s: src1Addr->dim_y 128
[C7x_1 ] 63.906317 s: src1Addr->stride_y 3968
[C7x_1 ] 63.906339 s: dstAddr->data_type 1
[C7x_1 ] 63.906361 s: dstAddr->dim_x 96
[C7x_1 ] 63.906383 s: dstAddr->dim_y 32
[C7x_1 ] 63.906406 s: dstAddr->stride_y 448
[C7x_1 ] 63.906422 s: End Layer Idx 6
[C7x_1 ] 63.908416 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle 50
[C7x_1 ] 63.908457 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908496 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908534 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908572 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908609 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908647 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908684 s: MMALIB_CNN_convolveBias_row_ixX_ixX_oxX_init :FAILED for subhandle -1
[C7x_1 ] 63.908770 s: Not enough memory to allocate intMemPtr in MSMC
[C7x_1 ] 63.908806 s: Warning: Trying to get scratch mem from DDR. Expect performance degradation!
[C7x_1 ] 63.908840 s: Link Id 2684354656, Number of TR required = 3
[C7x_1 ] 63.908868 s: ===================================================
[C7x_1 ] 63.908898 s: Link Id 2717909088, Number of TR required = 1
[C7x_1 ] 63.908926 s: ===================================================
[C7x_1 ] 63.908955 s: Link Id 2734686304, Number of TR required = 1
[C7x_1 ] 63.908982 s: ===================================================
[C7x_1 ] 63.909011 s: Link Id 2751463520, Number of TR required = 1
[C7x_1 ] 63.909038 s: ===================================================
[C7x_1 ] 63.909067 s: Link Id 2768240736, Number of TR required = 1
[C7x_1 ] 63.909094 s: ===================================================
[C7x_1 ] 63.910625 s: PREEMPTION: Adding a new priority object for targetPriority = 256, handle = 100000000
[C7x_1 ] 63.910685 s: PREEMPTION: Now total number of priority objects = 1 at priorityId = 256, with new memRec of base = 100a616
[C7x_1 ] 63.910742 s: PREEMPTION: Requesting context memory addr for handle 100000000, return Addr = b30f2348
[C7x_1 ] 63.910774 s: Print preEmption Hnadle during init stage :
[C7x_1 ] 63.910798 s: ProcTime, ctxSize, dataId
[C7x_1 ] 63.910825 s: 0.000, 6520, 0
[C7x_1 ] 64.910203 s: TIDL_process is started with handle : 100000000
[C7x_1 ] 64.910247 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256 is serviced
[C7x_1 ] 64.910294 s: PREEMPTION: Requesting LOCK for priroty object with handle = 100000000 and targetPriority 256
[C7x_1 ] 64.910349 s: PREEMPTION: Request of LOCK for priroty object with handle = 100000000 and targetPriority 256 is serviced wit0
[C7x_1 ] 64.910445 s: TIDL_activate is called with handle : 100000000 - Copying handle of size 20144 from 100000000 to 682d2000
[C7x_1 ] 64.910504 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256
[C7x_1 ] 64.910546 s: PREEMPTION: Requesting UNLOCK for priroty object and targetPriority 256 is serviced
[C7x_1 ] 64.910593 s: PREEMPTION: Requesting LOCK for priroty object with handle = 100000000 and targetPriority 256
[C7x_1 ] 64.910647 s: PREEMPTION: Request of LOCK for priroty object with handle = 100000000 and targetPriority 256 is serviced wit0
[C7x_1 ] 64.910682 s: Coreid 0 Layerid to execute = 2
[C7x_1 ] 64.910711 s: Core 0 Alg Process for Layer # - 2, layer type 41
[C7x_1 ] 64.910739 s: Processing Layer # - 2
[C7x_1 ] 64.910795 s: Core 0 End of Layer # - 2 with outPtrs[0] = 68200000
[C7x_1 ] 64.910825 s: Coreid 0 Layerid to execute = 3
[C7x_1 ] 64.910854 s: Core 0 Alg Process for Layer # - 3, layer type 43
[C7x_1 ] 64.910880 s: Processing Layer # - 3
[C7x_1 ] 64.911944 s: Core 0 End of Layer # - 3 with outPtrs[0] = 68000000
[C7x_1 ] 64.911974 s: Coreid 0 Layerid to execute = 4
[C7x_1 ] 64.912003 s: Core 0 Alg Process for Layer # - 4, layer type 41
[C7x_1 ] 64.912028 s: Processing Layer # - 4
[C7x_1 ] 64.912211 s: Core 0 End of Layer # - 4 with outPtrs[0] = 10002c400
[C7x_1 ] 64.912239 s: Coreid 0 Layerid to execute = 5
[C7x_1 ] 64.912268 s: Core 0 Alg Process for Layer # - 5, layer type 38
[C7x_1 ] 64.912293 s: Processing Layer # - 5
[C7x_1 ] 64.912324 s: Core 0 End of Layer # - 5 with outPtrs[0] = 10002c400
[C7x_1 ] 64.912351 s: Coreid 0 Layerid to execute = 6
[C7x_1 ] 64.912380 s: Core 0 Alg Process for Layer # - 6, layer type 1
[C7x_1 ] 64.912403 s: Processing Layer # - 6
[C7x_1 ] 64.912484 s: A0 =0x988 A1 =0x1
[C7x_1 ] 64.912497 s: A2 =0x1 A3 =0x1
[C7x_1 ] 64.912506 s: A4 =0x68093f40 A5 =0x1
[C7x_1 ] 64.912516 s: A6 =0xd60 A7 =0x6486a980
[C7x_1 ] 64.912527 s: A8 =0xb3109f90 A9 =0xb3109f94
[C7x_1 ] 64.912538 s: A10=0x18002100 A11=0x64800080
[C7x_1 ] 64.912549 s: A12=0x20 A13=0x6486a980
[C7x_1 ] 64.912559 s: A14=0x0 A15=0x0
[C7x_1 ] 64.912568 s: D0 =0x68093f40 D1 =0x8c0
[C7x_1 ] 64.912579 s: D2 =0x0 D3 =0xb310a6b0
[C7x_1 ] 64.912589 s: D4 =0x68094800 D5 =0x18000150
[C7x_1 ] 64.912599 s: D6 =0x18001fc0 D7 =0x18001e80
[C7x_1 ] 64.912610 s: D8 =0x68094800 D9 =0x0
[C7x_1 ] 64.912620 s: D10=0x0 D11=0x90000000
[C7x_1 ] 64.912630 s: D12=0x68000000 D13=0x68094800
[C7x_1 ] 64.912640 s: D14=0x6486a980 D15=0xb3109db8
[C7x_1 ] 64.912651 s: AM0=0x6b AM1=0x940
[C7x_1 ] 64.912661 s: AM2=0x0 AM3=0x1
[C7x_1 ] 64.912670 s: AM4=0x0 AM5=0x4890a20
[C7x_1 ] 64.912680 s: AM6=0x51b5e521 AM7=0x0
[C7x_1 ] 64.912690 s: AL0=0x460 AL1=0x1
[C7x_1 ] 64.912699 s: AL2=0x1 AL3=0x1
[C7x_1 ] 64.912708 s: AL4=0x8094800 AL5=0x10094800
[C7x_1 ] 64.912719 s: AL6=0x18094800 AL7=0x7ffffff
[C7x_1 ] 64.912730 s: P0=0xfffff P1=0xfffff
[C7x_1 ] 64.912739 s: P2=0x0 P3=0x0
[C7x_1 ] 64.912748 s: P4=0x0 P5=0xffffffff
[C7x_1 ] 64.912758 s: P6=0xffffffff P7=0xffffffff
[C7x_1 ] 64.912768 s: FPCR=0x10 FSR=0x10101012
[C7x_1 ] 64.912779 s: GFPGFR=0x700001d GPLY=0x0
[C7x_1 ] 64.912789 s:
[C7x_1 ] =0xb333fa40 [0]
[C7x_1 ] 64.912799 s:
[C7x_1 ] =0xb333fa40 [0]
[C7x_1 ] 64.912808 s: 0x4e60d109 [1]
[C7x_1 ] 64.912817 s: 0xcef9b017 [2]
[C7x_1 ] 64.912827 s: 0x4e97801b [3]
[C7x_1 ] 64.912836 s: 0x49a0b2a0 [4]
[C7x_1 ] 64.912845 s: 0x4ec32509 [5]
[C7x_1 ] 64.912854 s: 0xced75ff7 [6]
[C7x_1 ] 64.912863 s: 0x4c880142 [7]
[C7x_1 ] 64.912872 s: 0x0 [1]
[C7x_1 ] 64.912880 s: 0x0 [2]
[C7x_1 ] 64.912889 s: 0x40 [3]
[C7x_1 ] 64.912897 s: 0x40 [4]
[C7x_1 ] 64.912906 s: 0x0 [5]
[C7x_1 ] 64.912914 s: 0x0 [6]
[C7x_1 ] 64.912922 s: 0x1004000 [7]
[C7x_1 ] 64.912932 s:
[C7x_1 ] =0xb333f9c0 [0]
[C7x_1 ] 64.912942 s:
[C7x_1 ] =0xb333f9c0 [0]
[C7x_1 ] 64.912950 s: 0x24 [1]
[C7x_1 ] 64.912959 s: 0x1 [2]
[C7x_1 ] 64.912967 s: 0x460 [3]
[C7x_1 ] 64.912976 s: 0xe0 [4]
[C7x_1 ] 64.912984 s: 0x20 [5]
[C7x_1 ] 64.912993 s: 0x0 [6]
[C7x_1 ] 64.913001 s: 0x4405000 [7]
[C7x_1 ] 64.913010 s: 0x2 [1]
[C7x_1 ] 64.913018 s: 0x8000 [2]
[C7x_1 ] 64.913027 s: 0x40 [3]
[C7x_1 ] 64.913036 s: 0x40 [4]
[C7x_1 ] 64.913044 s: 0x40 [5]
[C7x_1 ] 64.913053 s: 0x0 [6]
[C7x_1 ] 64.913061 s: 0x4006000 [7]
[C7x_1 ] 64.913070 s:
[C7x_1 ] =0xb333f940 [0]
[C7x_1 ] 64.913080 s:
[C7x_1 ] =0xb333f940 [0]
[C7x_1 ] 64.913089 s: 0x12 [1]
[C7x_1 ] 64.913097 s: 0x12 [2]
[C7x_1 ] 64.913106 s: 0x12 [3]
[C7x_1 ] 64.913114 s: 0x12 [4]
[C7x_1 ] 64.913123 s: 0x12 [5]
[C7x_1 ] 64.913131 s: 0x12 [6]
[C7x_1 ] 64.913139 s: 0x12 [7]
[C7x_1 ] 64.913148 s: 0x18 [1]
[C7x_1 ] 64.913156 s: 0x18 [2]
[C7x_1 ] 64.913164 s: 0x18 [3]
[C7x_1 ] 64.913173 s: 0x18 [4]
[C7x_1 ] 64.913181 s: 0x18 [5]
[C7x_1 ] 64.913190 s: 0x18 [6]
[C7x_1 ] 64.913198 s: 0x18 [7]
[C7x_1 ] 64.913207 s:
[C7x_1 ] =0xb333f8c0 [0]
[C7x_1 ] 64.913216 s:
[C7x_1 ] =0xb333f8c0 [0]
[C7x_1 ] 64.913226 s: 0x220890e9 [1]
[C7x_1 ] 64.913235 s: 0x9c90144 [2]
[C7x_1 ] 64.913243 s: 0x8d56da21 [3]
[C7x_1 ] 64.913253 s: 0x4b00c105 [4]
[C7x_1 ] 64.913262 s: 0x8d182383 [5]
[C7x_1 ] 64.913271 s: 0x809b2382 [6]
[C7x_1 ] 64.913280 s: 0x1084094 [7]
[C7x_1 ] 64.913289 s: 0x7fffffff [1]
[C7x_1 ] 64.913298 s: 0x7fffffff [2]
[C7x_1 ] 64.913307 s: 0x7fffffff [3]
[C7x_1 ] 64.913316 s: 0x7fffffff [4]
[C7x_1 ] 64.913325 s: 0x7fffffff [5]
[C7x_1 ] 64.913335 s: 0x7fffffff [6]
[C7x_1 ] 64.913343 s: 0x7fffffff [7]
[C7x_1 ] 64.913353 s:
[C7x_1 ] VBL0=0xb333f840 [0]
[C7x_1 ] 64.913362 s:
[C7x_1 ] VBL1=0xb333f840 [0]
[C7x_1 ] 64.913372 s: 0x0 [1]
[C7x_1 ] 64.913380 s: 0x0 [2]
[C7x_1 ] 64.913389 s: 0x0 [3]
[C7x_1 ] 64.913397 s: 0x0 [4]
[C7x_1 ] 64.913405 s: 0x0 [5]
[C7x_1 ] 64.913413 s: 0x0 [6]
[C7x_1 ] 64.913422 s: 0x0 [7]
[C7x_1 ] 64.913430 s: 0x0 [1]
[C7x_1 ] 64.913438 s: 0x0 [2]
[C7x_1 ] 64.913446 s: 0x0 [3]
[C7x_1 ] 64.913455 s: 0x0 [4]
[C7x_1 ] 64.913463 s: 0x0 [5]
[C7x_1 ] 64.913471 s: 0x0 [6]
[C7x_1 ] 64.913480 s: 0x0 [7]
[C7x_1 ] 64.913488 s:
[C7x_1 ] VBL2=0xb333f7c0 [0]
[C7x_1 ] 64.913498 s:
[C7x_1 ] VBL3=0xb333f7c0 [0]
[C7x_1 ] 64.913508 s: 0x0 [1]
[C7x_1 ] 64.913516 s: 0x0 [2]
[C7x_1 ] 64.913524 s: 0x0 [3]
[C7x_1 ] 64.913532 s: 0x0 [4]
[C7x_1 ] 64.913541 s: 0x0 [5]
[C7x_1 ] 64.913549 s: 0x0 [6]
[C7x_1 ] 64.913557 s: 0x0 [7]
[C7x_1 ] 64.913565 s: 0x0 [1]
[C7x_1 ] 64.913574 s: 0x0 [2]
[C7x_1 ] 64.913582 s: 0x0 [3]
[C7x_1 ] 64.913590 s: 0x0 [4]
[C7x_1 ] 64.913598 s: 0x0 [5]
[C7x_1 ] 64.913607 s: 0x0 [6]
[C7x_1 ] 64.913615 s: 0x0 [7]
[C7x_1 ] 64.913623 s:
[C7x_1 ] =0xb333f740 [0]
[C7x_1 ] 64.913633 s:
[C7x_1 ] =0xb333f740 [0]
[C7x_1 ] 64.913642 s: 0x4000 [1]
[C7x_1 ] 64.913650 s: 0x4000 [2]
[C7x_1 ] 64.913660 s: 0x4000 [3]
[C7x_1 ] 64.913668 s: 0x4000 [4]
[C7x_1 ] 64.913677 s: 0x4000 [5]
[C7x_1 ] 64.913685 s: 0x4000 [6]
[C7x_1 ] 64.913694 s: 0x4000 [7]
[C7x_1 ] 64.913703 s: 0x0 [1]
[C7x_1 ] 64.913711 s: 0x0 [2]
[C7x_1 ] 64.913720 s: 0x0 [3]
[C7x_1 ] 64.913728 s: 0x0 [4]
[C7x_1 ] 64.913736 s: 0x0 [5]
[C7x_1 ] 64.913744 s: 0x0 [6]
[C7x_1 ] 64.913753 s: 0x0 [7]
[C7x_1 ] 64.913761 s:
[C7x_1 ] =0xb333f6c0 [0]
[C7x_1 ] 64.913771 s:
[C7x_1 ] VBL7=0xb333f6c0 [0]
[C7x_1 ] 64.913780 s: 0x4 [1]
[C7x_1 ] 64.913788 s: 0x4 [2]
[C7x_1 ] 64.913797 s: 0x4 [3]
[C7x_1 ] 64.913805 s: 0x4 [4]
[C7x_1 ] 64.913814 s: 0x4 [5]
[C7x_1 ] 64.913822 s: 0x4 [6]
[C7x_1 ] 64.913831 s: 0x4 [7]
[C7x_1 ] 64.913839 s: 0x7ff0 [1]
[C7x_1 ] 64.913847 s: 0x7ff0 [2]
[C7x_1 ] 64.913856 s: 0x7ff0 [3]
[C7x_1 ] 64.913865 s: 0x7ff0 [4]
[C7x_1 ] 64.913873 s: 0x7ff0 [5]
[C7x_1 ] 64.913882 s: 0x7ff0 [6]
[C7x_1 ] 64.913891 s: 0x7ff0 [7]
[C7x_1 ] 64.913900 s:
[C7x_1 ] VB0=0xb333fe40 [0]
[C7x_1 ] 64.913909 s:
[C7x_1 ] VB1=0xb333fe40 [0]
[C7x_1 ] 64.913919 s: 0x0 [1]
[C7x_1 ] 64.913927 s: 0x0 [2]
[C7x_1 ] 64.913935 s: 0x0 [3]
[C7x_1 ] 64.913944 s: 0x0 [4]
[C7x_1 ] 64.913952 s: 0x0 [5]
[C7x_1 ] 64.913960 s: 0x0 [6]
[C7x_1 ] 64.913968 s: 0x0 [7]
[C7x_1 ] 64.913977 s: 0x0 [1]
[C7x_1 ] 64.913985 s: 0x0 [2]
[C7x_1 ] 64.913993 s: 0x0 [3]
[C7x_1 ] 64.914001 s: 0x0 [4]
[C7x_1 ] 64.914010 s: 0x0 [5]
[C7x_1 ] 64.914018 s: 0x0 [6]
[C7x_1 ] 64.914026 s: 0x0 [7]
[C7x_1 ] 64.914034 s:
[C7x_1 ] VB2=0xb333fdc0 [0]
[C7x_1 ] 64.914043 s:
[C7x_1 ] =0xb333fdc0 [0]
[C7x_1 ] 64.914053 s: 0x0 [1]
[C7x_1 ] 64.914061 s: 0x1 [2]
[C7x_1 ] 64.914070 s: 0x0 [3]
[C7x_1 ] 64.914078 s: 0x0 [4]
[C7x_1 ] 64.914086 s: 0x0 [5]
[C7x_1 ] 64.914094 s: 0x0 [6]
[C7x_1 ] 64.914103 s: 0x0 [7]
[C7x_1 ] 64.914111 s: 0x24 [1]
[C7x_1 ] 64.914120 s: 0x1 [2]
[C7x_1 ] 64.914128 s: 0x480 [3]
[C7x_1 ] 64.914137 s: 0x4a0 [4]
[C7x_1 ] 64.914146 s: 0x0 [5]
[C7x_1 ] 64.914154 s: 0x0 [6]
[C7x_1 ] 64.914162 s: 0x5005001 [7]
[C7x_1 ] 64.914171 s:
[C7x_1 ] VB4=0xb333fd40 [0]
[C7x_1 ] 64.914181 s:
[C7x_1 ] =0xb333fd40 [0]
[C7x_1 ] 64.914190 s: 0x0 [1]
[C7x_1 ] 64.914198 s: 0x0 [2]
[C7x_1 ] 64.914207 s: 0x0 [3]
[C7x_1 ] 64.914215 s: 0x0 [4]
[C7x_1 ] 64.914224 s: 0x0 [5]
[C7x_1 ] 64.914232 s: 0x0 [6]
[C7x_1 ] 64.914240 s: 0x0 [7]
[C7x_1 ] 64.914248 s: 0x7060504 [1]
[C7x_1 ] 64.914257 s: 0xf0e0d0c [2]
[C7x_1 ] 64.914266 s: 0x17161514 [3]
[C7x_1 ] 64.914275 s: 0x1f1e1d1c [4]
[C7x_1 ] 64.914284 s: 0x27262524 [5]
[C7x_1 ] 64.914293 s: 0x2f2e2d2c [6]
[C7x_1 ] 64.914302 s: 0x37363534 [7]
[C7x_1 ] 64.914311 s:
[C7x_1 ] VB6=0xb333fcc0 [0]
[C7x_1 ] 64.914321 s:
[C7x_1 ] =0xb333fcc0 [0]
[C7x_1 ] 64.914330 s: 0x0 [1]
[C7x_1 ] 64.914338 s: 0x0 [2]
[C7x_1 ] 64.914347 s: 0x0 [3]
[C7x_1 ] 64.914355 s: 0x0 [4]
[C7x_1 ] 64.914363 s: 0x0 [5]
[C7x_1 ] 64.914372 s: 0x0 [6]
[C7x_1 ] 64.914380 s: 0x0 [7]
[C7x_1 ] 64.914388 s: 0x0 [1]
[C7x_1 ] 64.914396 s: 0x0 [2]
[C7x_1 ] 64.914405 s: 0x0 [3]
[C7x_1 ] 64.914413 s: 0x0 [4]
[C7x_1 ] 64.914421 s: 0x0 [5]
[C7x_1 ] 64.914429 s: 0x0 [6]
[C7x_1 ] 64.914438 s: 0x0 [7]
[C7x_1 ] 64.914446 s:
[C7x_1 ] =0xb333fc40 [0]
[C7x_1 ] 64.914455 s:
[C7x_1 ] =0xb333fc40 [0]
[C7x_1 ] 64.914464 s: 0x1 [1]
[C7x_1 ] 64.914473 s: 0x1 [2]
[C7x_1 ] 64.914481 s: 0x1 [3]
[C7x_1 ] 64.914489 s: 0x1 [4]
[C7x_1 ] 64.914498 s: 0x1 [5]
subgraph_0_tidl_io_1.bin
CTRL-A Z for help | 115200 8N1 | NOR | Minicom 2.8 | VT102 | Offline | ttyUSB0
it seems that this only happens if we use tidl_model_import.out to convert the model. We will focus on finding out the difference between edgeai and rtos way of importing. Please allow me some time for this.
Regards,
Adam
Hi Hongyao,
Thanks for your continuous attention to this issue.
I made a mistake here by setting all tensor to 16bits and it was incorrectly successful with edgeai tool:
I test it on 11.0.8.0 tidl with edgeai tidl tools. I cannot reproduce this issue.
Also the infer with rtos tool was also using the bin files created with edgeai 16bits:
I am also able to run it with rtos tool:
Now that I can reproduce this issue with both edgeai tool and rtos tool:
Using standard report format:
| Property | Details |
|---|---|
| Device | J784s4 |
| SDK Version | 11.0 |
| TIDL firmware version | 11_00_08_00 |
| TIDL Tools Version | 11_00_08_00 |
| Issue Category |
|
| Example AI model | https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/SimpleBev_5F00_OD.onnx |
| Compilation method |
|
| Compilation log | python3 onnxrt_ep.py -c -m gridsample16bit
Available execution providers : ['TIDLExecutionProvider', 'TIDLCompilationProvider', 'CPUExecutionProvider']
Running 1 Models - ['gridsample16bit']
Running_Model : gridsample16bit
Running shape inference on model ../../../models/public/girdsample16bit.onnx
tidl_tools_path = /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools
artifacts_folder = ../../../model-artifacts//gridsample16bit/artifacts
tidl_tensor_bits = 8
debug_level = 1
num_tidl_subgraphs = 16
num_tidl_subgraph_max_node = 0
enable_rt_multi_subgraph_support = 0
tidl_denylist =
tidl_denylist_layer_name =
tidl_denylist_layer_type =
tidl_allowlist_layer_name =
model_type =
tidl_calibration_accuracy_level = 7
tidl_calibration_options:num_frames_calibration = 2
tidl_calibration_options:bias_calibration_iterations = 5
mixed_precision_factor = -1.000000
model_group_id = 0
power_of_2_quantization = 2
ONNX QDQ Enabled = 0
enable_high_resolution_optimization = 0
pre_batchnorm_fold = 1
add_data_convert_ops = 3
output_feature_16bit_names_list = /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
m_params_16bit_names_list = /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
m_single_core_layers_names_list =
m_spatial_split_layers_names_list =
m_channel_split_layers_names_list =
Inference mode = 0
Number of cores = 1
reserved_compile_constraints_flag = 83886080
partial_init_during_compile = 0
packetize_mode = 0
enable_tfr_optimization = 0
ti_internal_reserved_1 =
========================= [Model Compilation Started] =========================
Model compilation will perform the following stages:
1. Parsing
2. Graph Optimization
3. Quantization & Calibration
4. Memory Planning
============================== [Version Summary] ==============================
-------------------------------------------------------------------------------
| TIDL Tools Version | 11_00_08_00 |
-------------------------------------------------------------------------------
| C7x Firmware Version | 11_00_08_00 |
-------------------------------------------------------------------------------
| Runtime Version | 1.15.0 |
-------------------------------------------------------------------------------
| Model Opset Version | 16 |
-------------------------------------------------------------------------------
============================== [Parsing Started] ==============================
[TIDL Import] [PARSER] WARNING: Network not identified as Object Detection network : (1) Ignore if network is not Object Detection network (2) If network is Object Detection network, please specify "model_type":"OD" as part of OSRT compilation options
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - GridSample, Node name - /bev_encoder/GridSample_5 -- [tidl_onnxRtImport_core.cpp, 626]
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Reshape, Node name - /bev_encoder/Reshape_18 -- [tidl_onnxRtImport_core.cpp, 626]
[TIDL Import] [PARSER] SUPPORTED: Layers type supported by TIDL --- layer type - Conv, Node name - /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv -- [tidl_onnxRtImport_core.cpp, 626]
------------------------- Subgraph Information Summary -------------------------
-------------------------------------------------------------------------------
| Core | No. of Nodes | Number of Subgraphs |
-------------------------------------------------------------------------------
| C7x | 3 | 1 |
| CPU | 0 | x |
-------------------------------------------------------------------------------
Running Runtimes GraphViz - /home/ht/edgeai/edgeai-tidl-tools/tools/AM69A/tidl_tools/tidl_graphVisualiser_runtimes.out ../../../model-artifacts//gridsample16bit/artifacts/allowedNode.txt ../../../model-artifacts//gridsample16bit/artifacts/tempDir/graphvizInfo.txt ../../../model-artifacts//gridsample16bit/artifacts/tempDir/runtimes_visualization.svg
============================= [Parsing Completed] =============================
TIDL_createStateImportFunc Started:
Compute on node : TIDLExecutionProvider_TIDL_0_0
0, GridSample, 2, 1, /bev_encoder/Reshape_15_output_0, /bev_encoder/GridSample_5_output_0
1, Reshape, 2, 1, /bev_encoder/GridSample_5_output_0, /bev_encoder/Reshape_18_output_0
2, Conv, 3, 1, /bev_encoder/Reshape_18_output_0, /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
Input tensor name - /bev_encoder/Reshape_15_output_0
Input tensor name - /bev_encoder/Unsqueeze_5_output_0
Output tensor name - /bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
In TIDL_onnxRtImportInit subgraph_name=subgraph_0
Layer 0, subgraph id subgraph_0, name=/bev_encoder/con_layer.0/con_layer.0.0/layer/layer.0/Conv_output_0
Layer 1, subgraph id subgraph_0, name=/bev_encoder/Reshape_15_output_0
Layer 2, subgraph id subgraph_0, name=/bev_encoder/Unsqueeze_5_output_0
==================== [Optimization for subgraph_0 Started] ====================
In TIDL_runtimesOptimizeNet: LayerIndex = 6, dataIndex = 5
----------------------------- Optimization Summary -----------------------------
--------------------------------------------------------------------------------
| Layer | Nodes before optimization | Nodes after optimization |
--------------------------------------------------------------------------------
| TIDL_TransposeLayer | 0 | 2 |
| TIDL_ConvolutionLayer | 1 | 1 |
| TIDL_GridSampleLayer | 1 | 1 |
--------------------------------------------------------------------------------
Total nodes in subgraph: 11
=================== [Optimization for subgraph_0 Completed] ===================
In TIDL_runtimesPostProcessNet
************ in TIDL_subgraphRtCreate ************
The soft limit is 10240
The hard limit is 10240
MEM: Init ... !!!
MEM: Init ... Done !!!
0.0s: VX_ZONE_INFO: Globally Enabled VX_ZONE_ERROR
0.5s: VX_ZONE_INFO: Globally Enabled VX_ZONE_WARNING
************ TIDL_subgraphRtCreate done ************
============= [Quantization & Calibration for subgraph_0 Started] =============
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles,
2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Sum of Layer Cycles 0
Sub Graph Stats 41.000000 1938259.000000 4840.000000
******* TIDL_subgraphRtInvoke done ********
******* In TIDL_subgraphRtInvoke ********
Layer, Layer Cycles,kernelOnlyCycles, coreLoopCycles,LayerSetupCycles,dmaPipeupCycles, dmaPipeDownCycles, PrefetchCycles,copyKerCoeffCycles,LayerDeinitCycles,LastBlockCycles, paddingTrigger, paddingWait,LayerWithoutPad,LayerHandleCopy, BackupCycles, RestoreCycles,Multic7xContextCopyCycles,
2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
4, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
6, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
8, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
9, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
Sum of Layer Cycles 0
Sub Graph Stats 33.000000 1919911.000000 783.000000
******* TIDL_subgraphRtInvoke done ********
In TIDL_runtimesPostProcessNet
-------- Running Calibration in Float Mode to Collect Tensor Statistics --------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [1 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [2 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [3 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [4 / 5]: ------------------
[=============================================================================] 100 %
------------------ Fixed-point Calibration Iteration [5 / 5]: ------------------
[=============================================================================] 100 %
==================== [Quantization & Calibration Completed] ====================
========================== [Memory Planning Started] ==========================
------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation
========================= [Memory Planning Completed] =========================
Rerunning network compiler...
========================== [Memory Planning Started] ==========================
------------------------- Network Compiler Traces ------------------------------
Successful Memory Allocation
Successful Workload Creation
========================= [Memory Planning Completed] =========================
======================== Subgraph Compiled Successfully ========================
Saving output tensor to ../../../output_binaries/
Completed_Model : 1, Name : gridsample16bit , Total time : 16241.92, Offload Time : 1929.09 , DDR RW MBs : 0, Output Image File : py_out_gridsample16bit_ADE_val_00001801.jpg, Output Bin File : py_out_gridsample16bit_ADE_val_00001801.bin
************ in TIDL_subgraphRtDelete ************
MEM: Deinit ... !!!
MEM: Alloc's: 27 alloc's of 413633405 bytes
MEM: Free's : 27 free's of 413633405 bytes
MEM: Open's : 0 allocs of 0 bytes
MEM: Deinit ... Done !!!
|
| Compilation artifacts | gridsample16bit.tar.gz |
| Inference method |
|
| Inference log |
|
| Inference artifacts |
Regards,
Adam
Hi
Though I think you are already aware, we have filed a Jira item --> TIDL 7924 for this issue. Just posting it here for traceability.
Warm regards,
Christina