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IND-COMMS-SDK: PHY link detect via LED_0

Tomoya Oyama
Intellectual 330 points
Part Number: IND-COMMS-SDK
Other Parts Discussed in Thread: AM2432

Tool/software:

Hello team,

I develop EtherCAT subdevice application with AM2432 and de83822.

Link detection works fine via MDIO, but not via the PHY's GPIO.

This is how I set it up.

However, not only will the link not be detected, but the link will not even be found.

Is there any other configuration required?

Best regard,

Oyama

  • 0
    TI__Expert 8995 points

    Hi,

    Tomoya Oyama said:
    However, not only will the link not be detected, but the link will not even be found.
    • Could you confirm if link detection works when Enhanced Link is disabled: 
      • #define ECAT_PHYUSERXLINK_IN                (false)
#define ECAT_PHYUSERXLINK_OUT               (false)
         
    • Additionally, just to confirm, the MDIO link status is being observed at MDIO Link Register (offset: 0x30090E4C), right? 

    Regards,
    Aaron 

  • 0 in reply to Aaron Thomas
    Intellectual 330 points

    Hi Aaron,

    Aaron Thomas said:
    Could you confirm if link detection works when Enhanced Link is disabled

    Yes.

    Aaron Thomas said:
    Additionally, just to confirm, the MDIO link status is being observed at MDIO Link Register (offset: 0x30090E4C), right?

    0x30090E4C was empty, but I saw 0x300B240C instead.

    The value is 0x02, but what is actually connected is only 0x01 on the IN side.

    Best regard,

    Oyama

  • 0 in reply to Tomoya Oyama
    TI__Expert 8995 points

    Hi,

    Tomoya Oyama said:
    Yes.

    Thank you for the confirmation. So the issue seems to be Enhanced Link configuration.

    Tomoya Oyama said:
    The value is 0x02, but what is actually connected is only 0x01 on the IN side.

    Maybe the link polarity is inversed such that before connecting the port, 0x300B240C was 0x03 and on connecting the IN port, it became 0x02 (bit0 reset). Or if the polarity is not inverted, then try configuring the PHY Address in Syscfg based on the link status in the MDIO Link Reg (that is, 1 for IN and 0 for OUT).

    Regards,
    Aaron

  • 0 in reply to Aaron Thomas
    Intellectual 330 points

    Hi Aaron,

    Since LEDCR(7)=1, ECAT_PHYPOLINVERT was set to TRUE.

    However, this did not work, so I rewrote EC_API_SLV_registerPhy() directly.

    As a result, the link on the In side was established and communication was possible, but the link on the Out side was no longer established.

    The settings for both PHYs are the same, so what should I check?

    Best regard,

    Oyama

  • 0 in reply to Tomoya Oyama
    TI__Expert 8995 points

    So to confirm the current status, you are able to scan on IN port but scanning fails for OUT port, right?

    The link status register behaviour is same for IN and OUT port, that is, the bits for IN and OUT ports are getting toggled but link detection fails for OUT port?

  • 0 in reply to Aaron Thomas
    Intellectual 330 points

    Hi Aaron,

    Aaron Thomas said:
    So to confirm the current status, you are able to scan on IN port but scanning fails for OUT port, right?

    Yes. 

    Both PHY IN and OUT BMSR values are 0x786d (Valid link established), but the master cannot scan second device OUT side.

    It behaves as if there is no device on the OUT side, and the master does not notice that there is no Second device.

    Best regard,

    Oyama

  • 0 in reply to Tomoya Oyama
    TI__Expert 8995 points

    Hi Oyama,

    Please test with the latest EtherCAT firmware (with link detection enhancement done within firmware) shared to you and update us of the status.

    Also, can you provide the complete ICSS MDIO Memory dump (0x300B2400 to 0x300B248C) and also the PHY Register values, when both, the IN and OUT ports are connected to the AM243x device.

    Regards,
    Aaron

  • 0 in reply to Aaron Thomas
    Intellectual 330 points

    Hi Aaron,

    I applied the update and set ECAT_PHYPOLINVERT back to FALSE (the actual waveform was also active low) and the link and EtherCAT communication now works.

    Aaron Thomas said:
    Also, can you provide the complete ICSS MDIO Memory dump (0x300B2400 to 0x300B248C) and also the PHY Register values, when both, the IN and OUT ports are connected to the AM243x device.

    In the Initial step, I have changed MDIO_POLL_EN_REG (0x300B2438) to 0.

    Best regard,

    Oyama

    phy0(IN) phy1(OUT)
    0x0000 0x3100 0x3100
    0x0001 0x786D 0x786D
    0x0002 0x2000 0x2000
    0x0003 0xA240 0xA240
    0x0004 0x01E1 0x01E1
    0x0005 0xC1E1 0xC1E1
    0x0006 0x000F 0x000F
    0x0007 0x2001 0x2001
    0x0008 0x4000 0x4000
    0x0009 0x0080 0x0080
    0x000A 0x0132 0x0132
    0x000B 0x1000 0x1000
    0x000C
    0x000D 0x401F 0x401F
    0x000E 0x0024 0x0024
    0x000F 0x0000 0x0000
    0x0010 0x0215 0x4215
    0x0011 0x0108 0x0108
    0x0012 0x6400 0x6400
    0x0013 0x2800 0x2800
    0x0014 0x0000 0x0000
    0x0015 0x0000 0x0000
    0x0016 0x0100 0x0100
    0x0017 0x0049 0x0049
    0x0018 0x0200 0x0200
    0x0019 0x8C20 0x8C21
    0x0025 0xC1E1 0xC1E1
  • +1 in reply to Tomoya Oyama
    TI__Expert 8995 points

    Hi,

    Tomoya Oyama said:
    I applied the update and set ECAT_PHYPOLINVERT back to FALSE (the actual waveform was also active low) and the link and EtherCAT communication now works.

    Thank you for the confirmation. Can we mark this thread as 'Resolved'?

    Tomoya Oyama said:
    In the Initial step, I have changed MDIO_POLL_EN_REG (0x300B2438) to 0.

    As mentioned in the TRM, recommend to set bit31 in MDIO_POLL_EN_REG to take care of the HW limitation:

    Additionally, since "Enable MDIO Manual Mode" is checked in your application, you can also monitor for MDIO_ALIVE_REG and MDIO_LINK_REG at 0x30090E48 and 0x30090E4C, respectively.

    Regards,
    Aaron

  • 0 in reply to Aaron Thomas
    Intellectual 330 points

    Hi Aaron,

    Is it recommended to enable polling in MDIO Manual Mode, In addition to Enhanced Link?

  • +1 in reply to Tomoya Oyama
    TI__Expert 8995 points

    Hi, 

    MDIO Manual Mode a workaround for the errata mentioned in the documentation I shared in my previous reply and this workaround is independent of Enhanced Link. When MDIO Manual Mode is enabled, you can use the emulated register space for reading the link/alive status and writing/reading to the PHY Register space. 
    The firmware loaded for the workaround will take care of the MDIO configuration based on Enhanced Link configuration from the application.

    Regards,
    Aaron