AM625-Q1: Could you tell me the PLL clock frequency variation for CAN in SoC.

Hi Ito,

I cannot find PLL drift to be characterized in the datasheet. I think that if MCU0_PLL was selected during chip design, then it should cover the CAN specific requirements.

I think all the requirements in 4) are related to external components like system clock crystal / external system clock source, or external MCAN clock source like below:

Regards,

Stan

Ito,

Can please you point me the document with requirements 4) ?

Thanks

Hello Ito,

Refer below the available measurement data:

Could you please provide the clock tolerance specification for the MAIN_PLL0_HSDIV4_CLKOUT PLL that clocks the MCAN0 peripheral.
We have reviewed the AM62x TRM and Clock Tree but haven't found this information.

We determined the 6-sigma frequency error of the PLL output (80 MHz) that is sourcing the MCAN controller by measuring N-cycle jitter over a period of forty 80MHz clock cycles, which represents one bit time when operating at 2Mbps. The frequency error was calculated by applying the worst-case N-cycle jitter to the nominal period of forty clock cycles, or one bit time. The maximum frequency error of a single bit across the entire process, voltage, and temperature operating range (-40 to 125 junction) was 0.022%.

We also measured the frequency error over a period that represents 10 bits at 2Mbps, which is the resynchronization period for MCAN. The maximum frequency error of the resynchronization period across the entire process, voltage, and temperature range (-40 to 125 junction) was 0.003%.

Apologies for reopening this ticket. Could you please also verify the following? We need measurements for both 5 Mbps and 500 kbps data rates, as our project configuration is 5 Mbps FD CAN.
I will need to check with the team that collected the data.

We determined the 6-sigma frequency error of the PLL output (80 MHz) that is sourcing the MCAN controller by measuring N-cycle jitter over a period of ten 80MHz clock cycles, which represents one bit time when operating at 8Mbps. The frequency error was calculated by applying the worst-case N-cycle jitter to the nominal period of forty clock cycles, or one bit time. The maximum frequency error of a single bit across the entire process, voltage, and temperature operating range (-40 to 125 junction) was 0.064%.
We also measured the frequency error over a period that represents 10 bits at 8Mbps, which is the resynchronization period for MCAN. The maximum frequency error of the resynchronization period across the entire process, voltage, and temperature range (-40 to 125 junction) was 0.010%.
We did not measure jitter for the operating condition that represents 5Mbps, but the result would be somewhere between the 8Mbps and 2Mbps values.

Note: We do not have any plans to measure jitter for any other operating conditions.  We did not collect data for a duration that represents two-bit periods because the error associated with a single bit represents the worst-case error for the peripheral.  The error associated to two bits would be between the single bit error and the 10-bit error.

Regards,

Sreenivasa

Hi Sreenivasa,

>Can please you point me the document with requirements 4) ?

This is request from OEM and this is checklist for CAN. So customer can't share this infomation with TI.

Best regards,

Ito