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Interfacing FPGA to AM3517 GPMC Bus.

Richard Rooney91887
Prodigy 20 points
Other Parts Discussed in Thread: AM3517

We are interfacing an FPGA to the GPMC bus of the AM3517.

We intend to use Synchronous read and write cycles.

During these cycles we expected GPMC_CLK to free-run.

However AM35x TRM seems to state that the clock only runs for the duration of the access and returns to an off state between cycles.

This means we continuously will have to waste clock cycles performing synchronization for each cycle.

It would be very convenient for us if this clock could be kept running continuously.

Is this possible ?

Regards,

Richard.

  • 0
    TI__Guru* 85990 points

    Hi Richard, just a note that this is the AM335x forum.  Since you are using AM3517, you should be posting to AM35x forums:  http://e2e.ti.com/support/dsp/sitara_arm174_microprocessors/f/416.aspx

    There is no way to free run the GPMC_CLK.  A couple of ideas to get around this:

    You may be able to adjust the CONFIG registers to provide a few clocks before the memory cycle begins to help with synchronization.  You can also use the SYS_CLKOUT2, which is synchronous to GPMC_CLK, but not balanced coming out of the chip.  This may require you to add margin in your timings to account for the clocks being slightly out of phase.

    Regards,

    James

     

  • 0 in reply to JJD
    Expert 1435 points

    So this means that the control signals are not synchronous to SYS_CLKOUT2, right?