AM67: eMMC interface capacitance

Keisuke Nakano

Part Number: AM67

Tool/software:

Hi Support team,

MMC timing conditions are described on table 6-82. Can you please let us know what does this C_L output load capacitance mean ?

6pF and 12pF capacitance means device (package) only or this include device and trace?

eMMC spec below says C_L is:

C_L = C_HOST+ C_BUS + C_DEVICE

Thanks,
Nakano

6 months ago

0 Matt Park 6 months ago

TI__Expert 3150 points

Hi Nakano,

Checking with other experts to see if these values account for trace as well as device. Will reply back shortly.

Best Regards,

Matt

0 Keisuke Nakano 6 months ago in reply to Matt Park

TI__Intellectual 2525 points

Hi Matt,

Any update?

Thanks,
Nakano

0 Matt Park 5 months ago in reply to Keisuke Nakano

TI__Expert 3150 points

Hi Nakano,

Keisuke Nakano said:
6pF and 12pF capacitance means device (package) only or this include device and trace?

I believe the values you highlighted only account for the device. Trace length mismatch can be accounted for with values of trace delay and trace delay mismatch also shown in that table.

Best,

Matt

0 Keisuke Nakano 5 months ago in reply to Matt Park

TI__Intellectual 2525 points

Hi Matt,

This is very important, Please check and make sure C-L (output load capacitance) on the datasheet is C-HOST capacitance of the standard.

Thanks,
Nakano

0 Matt Park 5 months ago in reply to Keisuke Nakano

TI__Expert 3150 points

Hi Nakano,

I have confirmed with other experts. The C-L in our datasheet indicates the min/max limits on the sum of C-BUS and C-DEVICE.

Best Regards,

Matt

0 Keisuke Nakano 5 months ago in reply to Matt Park

TI__Intellectual 2525 points

Hi Matt,

Thanks for the confirmation. But if The C-L in the data sheet is sum of C-BUS and C-DEVICE, then this introduces another issue. Now our C-L is max 6pF. when look at C-DEVICE on JEDEC standard below, C-DVICE could be max 6pF and in this case there is no room for C-BUS.

C-L = C-BUS + C-DEVICE

6pF = 0pF + 6pF

Can you check how customer design their board in this case?

Thanks,
Nakano

0 Keisuke Nakano 5 months ago in reply to Keisuke Nakano

TI__Intellectual 2525 points

Hi Matt,

Any updates on this?

Thanks,
Nakano

0 Matt Park 5 months ago in reply to Keisuke Nakano

TI__Expert 3150 points

Hi Nakano,

This shouldn't be a problem for all other modes other than HS400.

Per our datasheet, the 6pF limit is only for HS400 mode. However, HS400 mode is not supported on AM67 per the device errata. HS200 mode and lower support up to 12pF.

Best Regards,

Matt

0 Keisuke Nakano 5 months ago in reply to Matt Park

TI__Intellectual 2525 points

Hi Matt,

Thanks for the clarification on HS400.

As for other modes, from AM67 datasheet;

C-L = C-BUS + C-DEVICE = 12pF

From JEDEC spec sheet;

C-L = C-HOST + C-BUS + C-DEVICE = 30pF

So, C-Host =AM67 capacitance becomes 18pF. AM67 capacitance is this big?

Thanks,
Nakano

0 Matt Park 5 months ago in reply to Keisuke Nakano

TI__Expert 3150 points

Hi Nakano,

Keisuke Nakano said:
So, C-Host =AM67 capacitance becomes 18pF. AM67 capacitance is this big?

30pF would be the max for C-L, so C-Host is not necessarily that big.

Also the other requirement you outlined in red is that the sum of host and bus cannot exceed 20pF.

So if C-L = C-BUS + C-DEVICE = 12pF where C-L = 12pF and C-DEVICE = 6pF, then C-BUS = 6pF.

If C-HOST + C-BUS <= 20pF, then C-HOST <= 14pF.

Best Regards,

Matt

Processors

Processors forum

AM67: eMMC interface capacitance