PROCESSOR-SDK-AM437X: How to config u-boot to support 16-bit width NAND flash in Am437x SDK

user5926475

Part Number: PROCESSOR-SDK-AM437X
Other Parts Discussed in Thread: TPS65218

Tool/software:

Hi,

we have been using the Am437X board card with NAND as the MTD system for a long time. Recently, we aim to improve the system's boot time, so we replaced the original 512x8-bit NAND (8-bit width,S34ML04G200TFI000) with 256x16-bit (16-bit width) NAND(MT29F4G16ABADAWP), hoping to increase the bit width to enhance read and write speeds.

We Compiled and downloaded u-boot-spl.bin to the board via serial port (xmodem):

Transferring u-boot-spl.bin...

100% 123 KB 9 KB/s 00:00:13 0 Errors

However, when we downloaded u-boot.img to the board, an error occurred:

OMAP-ELM: uncorrectable ECC errors

Transferring u-boot.img...

100% 595 KB 3 KB/s 00:02:29 0 Errors

xyzModem - CRC mode, 4769(SOH)/0(STX)/0(CAN) packets, 4 retries

Loaded 610096 bytes

U-Boot 2018.01-00444-ge782a78-dirty (Jul 16 2025 - 10:43:05 +0800)

CPU : AM437X-GP rev 1.2

Model: TI AM437x GP EVM

DRAM: 1 GiB

PMIC: TPS65218

NAND: 512 MiB

MMC: OMAP SD/MMC: 0

omap-elm: uncorrectable ECC errors

…

The SDK is ti-sdk-rt-am437x-evm-05.03.00.07.

We configure in u-boot:

1） Am43xx_evm_defconfig:CONFIG_SYS_NAND_BUSWIDTH_16BIT=y

2) In Am437x-gp-evm.dts, added: nand_flash_x8:

0x20 (PIN_INPUT | MUX_MODE0) /* gpmc_ad0.gpmc_ad8 */

0x24 (PIN_INPUT | MUX_MODE0) /* gpmc_ad1.gpmc_ad9 */

0x28 (PIN_INPUT | MUX_MODE0) /* gpmc_ad2.gpmc_ad10 */

0x2c (PIN_INPUT | MUX_MODE0) /* gpmc_ad3.gpmc_ad11 */

0x30 (PIN_INPUT | MUX_MODE0) /* gpmc_ad4.gpmc_ad12 */

0x34 (PIN_INPUT | MUX_MODE0) /* gpmc_ad5.gpmc_ad13 */

0x38 (PIN_INPUT | MUX_MODE0) /* gpmc_ad6.gpmc_ad14 */

0x3c (PIN_INPUT | MUX_MODE0) /* gpmc_ad7.gpmc_ad15 */

Meanwhile, change nand-bus-width=<8> to <16>:

&gpmc {

status = "okay";

pinctrl-names = "default";

pinctrl-0 = <&nand_flash_x8>;

ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */

nand@0,0 {

reg = <0 0 4>; /* device IO registers */

ti,nand-ecc-opt = "bch16";

ti,elm-id = <&elm>;

nand-bus-width = <16>; //<8>;

gpmc,device-width = <1>;

…

Is there anything else that needs to be configured or changed?

Best Regard!

Dudechao

2 months ago

0 user5926475 2 months ago

Intellectual 270 points

From the NAND(MT29F4G16ABADAWP) datasheet I cann't know how to define following definition in am43xx_evm.h:

/* NAND support */
#ifdef CONFIG_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64 //128
#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \
CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, \
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, \
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, \
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, \
60, 61, 62, 63, 64, 65, 66, 67, 68, 69, \
70, 71, 72, 73, 74, 75, 76, 77, 78, 79, \
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, \
90, 91, 92, 93, 94, 95, 96, 97, 98, 99, \
100, 101, 102, 103, 104, 105, \
}
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 26
#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x00180000
/* NAND: SPL related configs */MT29F8G08ADADAH4D.PDF
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x00300000 /* kernel offset */
#endif

Could someone please take a look? Thank you ver much! The attachment is our datasheet.

0 Hong Guan64 2 months ago in reply to user5926475

TI__Guru 69070 points

Based on the attached nand datasheet, "Page size x8: 2112 bytes (2048 + 64 bytes)"
=> BCH8 should be selected instead of BCH16
https://www.kernel.org/doc/Documentation/devicetree/bindings/mtd/gpmc-nand.txt
We've AM335x GP EVM, which has the nand device with "page size: 2048, OOB size: 64"
I'd recommend refer to gpmc-nand configuration files for AM335x EVM, for example, starting with
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/configs/am335x_evm_defconfig?h=11.01.05
https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/include/configs/am335x_evm.h?h=11.01.05
...
Best,
-Hong

0 user5926475 2 months ago in reply to Hong Guan64

Intellectual 270 points

Hong,

Thank you for your reply!
Based on the information you provided, we have adjusted the parameters related to NAND configuration in the file below:
1) Modifications have been made in am437x_evm.h:
#define CONFIG_SYS_NAND_PAGE_SIZE 2048
#define CONFIG_SYS_NAND_OOBSIZE 64
#define CONFIG_SYS_NAND_BLOCK_SIZE 0x20000
#define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \
10, 11, 12, 13, 14, 15, 16, 17, \
18, 19, 20, 21, 22, 23, 24, 25, \
26, 27, 28, 29, 30, 31, 32, 33, \
34, 35, 36, 37, 38, 39, 40, 41, \
42, 43, 44, 45, 46, 47, 48, 49, \
50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE 512
#define CONFIG_SYS_NAND_ECCBYTES 14

/* NAND support */
#ifdef CONFIG_NAND
/* NAND: device related configs */
#define CONFIG_SYS_NAND_PAGE_SIZE	2048
#define CONFIG_SYS_NAND_OOBSIZE		64 //128
#define CONFIG_SYS_NAND_BLOCK_SIZE	(128*1024)
#define CONFIG_SYS_NAND_PAGE_COUNT	(CONFIG_SYS_NAND_BLOCK_SIZE / \
					 CONFIG_SYS_NAND_PAGE_SIZE)
#define CONFIG_SYS_NAND_5_ADDR_CYCLE
/* NAND: driver related configs */
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_NAND_OMAP_ECCSCHEME	OMAP_ECC_BCH16_CODE_HW
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	NAND_LARGE_BADBLOCK_POS
#define CONFIG_SYS_NAND_ECCPOS	{ 2, 3, 4, 5, 6, 7, 8, 9, \
					 10, 11, 12, 13, 14, 15, 16, 17, \
					 18, 19, 20, 21, 22, 23, 24, 25, \
					 26, 27, 28, 29, 30, 31, 32, 33, \
					 34, 35, 36, 37, 38, 39, 40, 41, \
					 42, 43, 44, 45, 46, 47, 48, 49, \
					 50, 51, 52, 53, 54, 55, 56, 57, }
#define CONFIG_SYS_NAND_ECCSIZE		512
#define CONFIG_SYS_NAND_ECCBYTES	14 //26
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x00180000
/* NAND: SPL related configs */
/* NAND: SPL falcon mode configs */
#ifdef CONFIG_SPL_OS_BOOT
#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS	0x00300000 /* kernel offset */
#endif
#define NANDARGS \
	"mtdids=" CONFIG_MTDIDS_DEFAULT "\0" \
	"mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
	"nandargs=setenv bootargs console=${console} " \
		"${optargs} " \
		"root=${nandroot} " \
		"rootfstype=${nandrootfstype}\0" \
	"nandroot=ubi0:rootfs rw ubi.mtd=NAND.file-system,2048\0" \
	"nandrootfstype=ubifs rootwait=1\0" \
	"nandboot=echo Booting from nand ...; " \
		"run nandargs; " \
		"nand read ${fdtaddr} NAND.u-boot-spl-os; " \
		"nand read ${loadaddr} NAND.kernel; " \
		"bootz ${loadaddr} - ${fdtaddr}\0"
#define NANDBOOT			"run nandboot; "
#else /* !CONFIG_NAND */
#define NANDARGS
#define NANDBOOT
#endif /* CONFIG_NAND */

2) Modify the following in am437x-gp-evm.dts:
&gpmc {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&nand_flash_x8>;
ranges = <0 0 0 0x01000000>; /* minimum GPMC partition = 16MB */
nand@0,0 {
reg = <0 0 4>; /* device IO registers */
ti,nand-ecc-opt ="bch8";// "bch16";
ti,elm-id = <&elm>;
nand-bus-width = <16>; //<8>;
gpmc,device-width = <1>;
…

&elm {
	status = "okay";
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x8>;
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		reg = <0 0 4>;		/* device IO registers */
		ti,nand-ecc-opt ="bch8";// "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>; //<8>;
		gpmc,device-width = <1>;
		gpmc,sync-clk-ps = <0>;
		gpmc,cs-on-ns = <0>;
		gpmc,cs-rd-off-ns = <40>;
		gpmc,cs-wr-off-ns = <40>;
		gpmc,adv-on-ns = <0>;
		gpmc,adv-rd-off-ns = <25>;
		gpmc,adv-wr-off-ns = <25>;
		gpmc,we-on-ns = <0>;
		gpmc,we-off-ns = <20>;
		gpmc,oe-on-ns = <3>;
		gpmc,oe-off-ns = <30>;
		gpmc,access-ns = <30>;
		gpmc,rd-cycle-ns = <40>;
		gpmc,wr-cycle-ns = <40>;
		gpmc,wait-pin = <0>;
		gpmc,bus-turnaround-ns = <0>;
		gpmc,cycle2cycle-delay-ns = <0>;
		gpmc,clk-activation-ns = <0>;
		gpmc,wait-monitoring-ns = <0>;
		gpmc,wr-access-ns = <40>;
		gpmc,wr-data-mux-bus-ns = <0>;
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x000c0000 0x00040000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00100000 0x00080000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x00180000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x00280000 0x00040000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x002c0000 0x00040000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00300000 0x00700000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x1f600000>;
		};
	};
};

&dss {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_pins>;

	port {
		dpi_out: endpoint@0 {
			remote-endpoint = <&lcd_in>;
			data-lines = <24>;
		};
	};
};

&dcan0 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan0_default>;
	status = "okay";
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_default>;
	status = "okay";
};

&vpfe0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&vpfe0_pins_default>;
	pinctrl-1 = <&vpfe0_pins_sleep>;

	port {
		vpfe0_ep: endpoint {
			remote-endpoint = <&ov2659_1>;
			ti,am437x-vpfe-interface = <0>;
			bus-width = <8>;
			hsync-active = <0>;
			vsync-active = <0>;
		};
	};
};

3）am43xx_evm_defconfig is：

CONFIG_ARM=y
CONFIG_ARCH_OMAP2PLUS=y
CONFIG_TI_COMMON_CMD_OPTIONS=y
CONFIG_SYS_MALLOC_F_LEN=0x2000
CONFIG_AM43XX=y
CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
CONFIG_SPL_LOAD_FIT=y
CONFIG_SYS_EXTRA_OPTIONS="CONS_INDEX=1"
CONFIG_SYS_CONSOLE_INFO_QUIET=y
CONFIG_VERSION_VARIABLE=y
CONFIG_SPL=y
CONFIG_SPL_ETH_SUPPORT=y
CONFIG_SPL_MTD_SUPPORT=y
CONFIG_SPL_NET_SUPPORT=y
CONFIG_SPL_NET_VCI_STRING="AM43xx U-Boot SPL"
CONFIG_SPL_OS_BOOT=y
CONFIG_SPL_USB_GADGET_SUPPORT=y
CONFIG_SPL_USBETH_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_SPL=y
CONFIG_CMD_SPL_NAND_OFS=0x00100000
CONFIG_CMD_SPL_WRITE_SIZE=0x40000
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_NAND=y
# CONFIG_CMD_SETEXPR is not set
CONFIG_CMD_MTDPARTS=y
CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:256k(NAND.SPL),256k(NAND.SPL.backup1),256k(NAND.SPL.backup2),256k(NAND.SPL.backup3),512k(NAND.u-boot-spl-os),1m(NAND.u-boot),256k(NAND.u-boot-env),256k(NAND.u-boot-env.backup1),7m(NAND.kernel),-(NAND.file-system)"
CONFIG_ISO_PARTITION=y
CONFIG_OF_CONTROL=y
CONFIG_OF_LIST="am437x-gp-evm am437x-sk-evm am43x-epos-evm am437x-idk-evm"
CONFIG_ENV_IS_IN_NAND=y
CONFIG_DM=y
# CONFIG_BLK is not set
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_DM_GPIO=y
CONFIG_DM_MMC=y
CONFIG_MMC_OMAP_HS=y
CONFIG_NAND=y
CONFIG_SYS_NAND_BUSWIDTH_16BIT=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PHYLIB=y
# CONFIG_DM_ETH is not set
CONFIG_NETDEVICES=y
CONFIG_PHY_GIGE=y
CONFIG_DM_SERIAL=y
CONFIG_SYS_NS16550=y
CONFIG_TI_QSPI=y
CONFIG_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_XHCI_DWC3=y
CONFIG_USB_DWC3=y
CONFIG_USB_DWC3_GADGET=y
CONFIG_USB_DWC3_OMAP=y
CONFIG_USB_DWC3_PHY_OMAP=y
CONFIG_USB_STORAGE=y
CONFIG_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0403
CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_USB_ETHER=y

Other definitions remain the same as those for the original 8-bit width NAND.

we compile: 1) make CROSS_COMPILE=arm-linux-gnueabihf- am43xx_evm_config
2） make CROSS_COMPILE=arm-linux-gnueabihf- -j4
After downloading the generated u-boot.img via serial port, I still encounter the same error "omap-elm: uncorrectable ECC errors" when reading and writing to the NAND.
Could you please help us identify any potential issues? Many thanks for your help!

Best Regard！

Dudechao

0 user5926475 2 months ago in reply to user5926475

Intellectual 270 points

Hong,

Hello!
I modified the NAND read and write timing according to the information you recommended in DTS. After recompiling and downloading, an insufficient OOB error occurred:
U-Boot 2018.01-00444-ge782a78-dirty (Jul 18 2025 - 13:32:33 +0800)
CPU : AM437X-GP rev 1.2
Model: TI AM437x GP EVM
DRAM: 1 GiB
PMIC: TPS65218
NAND: nand: error: insufficient OOB: require=106
0 MiB
MMC: OMAP SD/MMC: 0
*** Error - No Valid Environment Area found
*** Warning - bad env area, using default environment
The above information is for your reference!
Thank you.

the am437x-gp-evm.dts modified is

gpmc,sync-clk-ps = <0>;
gpmc,cs-on-ns = <0>;
gpmc,cs-rd-off-ns = <44>;
gpmc,cs-wr-off-ns = <44>;
gpmc,adv-on-ns = <6>;
gpmc,adv-rd-off-ns = <34>;
gpmc,adv-wr-off-ns = <44>;
gpmc,we-off-ns = <40>;
gpmc,oe-off-ns = <54>;
gpmc,access-ns = <64>;
gpmc,rd-cycle-ns = <82>;
gpmc,wr-cycle-ns = <82>;
gpmc,wr-access-ns = <40>;
gpmc,wr-data-mux-bus-ns = <0>;

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x8>;
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		reg = <0 0 4>;		/* device IO registers */
		ti,nand-ecc-opt ="bch8";// "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>; 
		gpmc,device-width = <1>;
		
				
		gpmc,wait-pin = <0>;

			gpmc,sync-clk-ps = <0>;
			gpmc,cs-on-ns = <0>;
			gpmc,cs-rd-off-ns = <44>;
			gpmc,cs-wr-off-ns = <44>;
			gpmc,adv-on-ns = <6>;
			gpmc,adv-rd-off-ns = <34>;
			gpmc,adv-wr-off-ns = <44>;
			gpmc,we-off-ns = <40>;
			gpmc,oe-off-ns = <54>;
			gpmc,access-ns = <64>;
			gpmc,rd-cycle-ns = <82>;
			gpmc,wr-cycle-ns = <82>;
			gpmc,wr-access-ns = <40>;
			gpmc,wr-data-mux-bus-ns = <0>;
		
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x000c0000 0x00040000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00100000 0x00080000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x00180000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x00280000 0x00040000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x002c0000 0x00040000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00300000 0x00700000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x1f600000>;
		};
	};
};

&dss {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_pins>;

	port {
		dpi_out: endpoint@0 {
			remote-endpoint = <&lcd_in>;
			data-lines = <24>;
		};
	};
};

&dcan0 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan0_default>;
	status = "okay";
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_default>;
	status = "okay";
};

&vpfe0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&vpfe0_pins_default>;
	pinctrl-1 = <&vpfe0_pins_sleep>;

	port {
		vpfe0_ep: endpoint {
			remote-endpoint = <&ov2659_1>;
			ti,am437x-vpfe-interface = <0>;
			bus-width = <8>;
			hsync-active = <0>;
			vsync-active = <0>;
		};
	};
};

&gpmc {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&nand_flash_x8>;
	ranges = <0 0 0 0x01000000>;	/* minimum GPMC partition = 16MB */
	nand@0,0 {
		reg = <0 0 4>;		/* device IO registers */
		ti,nand-ecc-opt ="bch8";// "bch16";
		ti,elm-id = <&elm>;
		nand-bus-width = <16>; 
		gpmc,device-width = <1>;
		
				
		gpmc,wait-pin = <0>;

			gpmc,sync-clk-ps = <0>;
			gpmc,cs-on-ns = <0>;
			gpmc,cs-rd-off-ns = <44>;
			gpmc,cs-wr-off-ns = <44>;
			gpmc,adv-on-ns = <6>;
			gpmc,adv-rd-off-ns = <34>;
			gpmc,adv-wr-off-ns = <44>;
			gpmc,we-off-ns = <40>;
			gpmc,oe-off-ns = <54>;
			gpmc,access-ns = <64>;
			gpmc,rd-cycle-ns = <82>;
			gpmc,wr-cycle-ns = <82>;
			gpmc,wr-access-ns = <40>;
			gpmc,wr-data-mux-bus-ns = <0>;
		
		/* MTD partition table */
		/* All SPL-* partitions are sized to minimal length
		 * which can be independently programmable. For
		 * NAND flash this is equal to size of erase-block */
		#address-cells = <1>;
		#size-cells = <1>;
		partition@0 {
			label = "NAND.SPL";
			reg = <0x00000000 0x00040000>;
		};
		partition@1 {
			label = "NAND.SPL.backup1";
			reg = <0x00040000 0x00040000>;
		};
		partition@2 {
			label = "NAND.SPL.backup2";
			reg = <0x00080000 0x00040000>;
		};
		partition@3 {
			label = "NAND.SPL.backup3";
			reg = <0x000c0000 0x00040000>;
		};
		partition@4 {
			label = "NAND.u-boot-spl-os";
			reg = <0x00100000 0x00080000>;
		};
		partition@5 {
			label = "NAND.u-boot";
			reg = <0x00180000 0x00100000>;
		};
		partition@6 {
			label = "NAND.u-boot-env";
			reg = <0x00280000 0x00040000>;
		};
		partition@7 {
			label = "NAND.u-boot-env.backup1";
			reg = <0x002c0000 0x00040000>;
		};
		partition@8 {
			label = "NAND.kernel";
			reg = <0x00300000 0x00700000>;
		};
		partition@9 {
			label = "NAND.file-system";
			reg = <0x00a00000 0x1f600000>;
		};
	};
};

&dss {
	status = "ok";

	pinctrl-names = "default";
	pinctrl-0 = <&dss_pins>;

	port {
		dpi_out: endpoint@0 {
			remote-endpoint = <&lcd_in>;
			data-lines = <24>;
		};
	};
};

&dcan0 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan0_default>;
	status = "okay";
};

&dcan1 {
	pinctrl-names = "default";
	pinctrl-0 = <&dcan1_default>;
	status = "okay";
};

&vpfe0 {
	status = "okay";
	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&vpfe0_pins_default>;
	pinctrl-1 = <&vpfe0_pins_sleep>;

	port {
		vpfe0_ep: endpoint {
			remote-endpoint = <&ov2659_1>;
			ti,am437x-vpfe-interface = <0>;
			bus-width = <8>;
			hsync-active = <0>;
			vsync-active = <0>;
		};
	};
};

Best Regard

Dudechao

0 Hong Guan64 2 months ago in reply to user5926475

TI__Guru 69070 points

user5926475 said:
NAND: nand: error: insufficient OOB: require=106

The error is most likely due to the incorrect BCH scheme vs OOB size
I spotted one error from your reply yesterday.
>>>>
#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_BCH16_CODE_HW
<<<<
I'd recommend take AM335x EVM gpmc-nand configuration files as reference, and cross-check your modifications for your board.
Best,
-Hong

0 user5926475 2 months ago in reply to Hong Guan64

Intellectual 270 points

Hong,

Hello!
This is fine now . Thank you very much for your support!

Thank you!

Dudechao

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