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AM623: Single-Link OLDI panel problem

Part Number: AM623

Tool/software:

I set the panel to OLDI LVDS on the am62x. The panel is single-link. However, after setting, the image is displayed only on the left side of the LCD. The image is displayed in full, but on the left side. Why is this? Here is a part of the device tree.

    panel-lvds {
        compatible = "panel-lvds";
        backlight = <&backlight>;
        data-mapping = "jeida-24";
        rotation = <0>;

        width-mm = <95>;
        height-mm = <55>;

        status = "okay";

        panel-timing {
            clock-frequency = <25000000>;
            hactive = <800>;
            vactive = <480>;
            hback-porch = <8>;
            hfront-porch = <8>;
            hsync-len = <4>;
            vback-porch = <16>;
            vfront-porch = <16>;
            vsync-len = <4>;
            de-active = <1>;
            pixelclk-active = <1>;
        };

        port {
            panel_input: endpoint {
                remote-endpoint = <&oldi0_output>;
            };
        };
    };

    backlight: ecap1-backlight {
        compatible = "pwm-backlight";
        pwms = <&ecap1 0 1000000 0>;
        brightness-levels = <0 64 128 192 255>;
        default-brightness-level = <4>;
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_backlight>;
        status = "okay";
    };

 &oldi0 {
    status = "okay";
};

&oldi0_ports {
    #address-cells = <1>;
    #size-cells = <0>;

    // DSS → OLDI0
    port@0 {
        reg = <0>;
        oldi0_input: endpoint {
            remote-endpoint = <&dss_to_oldi>;
        };
    };

    // OLDI0 → Panel
    port@1 {
        reg = <1>;
        oldi0_output: endpoint {
            remote-endpoint = <&panel_input>;
        };
    };
};

&dss_ports {
    #address-cells = <1>;
    #size-cells = <0>;

    /* port@0: OLDI output */
    port@0 {
        reg = <0>;
        dss_to_oldi: endpoint {
            remote-endpoint = <&oldi0_input>;
        };
    };
};

&ecap1 {
    status = "okay";
};

        oldi-txes {
            #address-cells = <1>;
            #size-cells = <0>;

            oldi0: oldi@0 {
                reg = <0>;
                clocks = <&k3_clks 186 0>;
                clock-names = "s_clk";
                /*ti,companion-oldi = <&oldi1>; */
                ti,oldi-io-ctrl = <&dss_oldi_io_ctrl>;
                status = "disabled";

                oldi0_ports: ports {
                };
            };

            /*oldi1: oldi@1 {
                reg = <1>;
                ti,secondary-oldi;
                status = "disabled";

                oldi1_ports: ports {
                };
            };*/
        };

        dss_ports: ports {
            #address-cells = <1>;
            #size-cells = <0>;
        };
    };

  • Hi,
    We currently do not have a working refernce with "panel-lvds".

    Can you please try using "panel-simple" as shown in https://git.ti.com/cgit/ti-linux-kernel/ti-linux-kernel/tree/arch/arm64/boot/dts/ti/k3-am625-sk-microtips-mf101hie-panel.dtso?h=ti-linux-6.12.y.

    You may drop 'dual-lvds-odd-pixels' and 'dual-lvds-even-pixels' flags for single link OLDI. Panel timings can be specified in fresh node within "panel-simple.c".

  • I changed code and device tree according to the URL, but still same. Could you present some situations that the image is displayed only on the left side of the LCD?

    static const struct drm_display_mode my_mode = {
        .clock = 25000,
        .hdisplay = 800,
        .hsync_start = 800 + 8,
        .hsync_end = 800 + 8 + 4,
        .htotal = 800 + 8 + 4 + 8,
        .vdisplay = 480,
        .vsync_start = 480 + 16,
        .vsync_end = 480 + 16 + 4,
        .vtotal = 480 + 16 + 4 + 16,
    };
    
    static const struct panel_desc my_panel = {
        .modes = &my_mode,
        .bpc = 8,
        .num_modes = 1,
        .size = {
            .width = 95,
            .height = 55,
        },
        .delay = {
            .prepare = 10,
            .disable = 10,
            .enable = 20,
            .unprepare = 5,
        },
        .bus_flags = DRM_BUS_FLAG_DE_HIGH,
        .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA,
        .connector_type = DRM_MODE_CONNECTOR_LVDS,
    };

    #else
        panel {
            compatible = "pna,pna-panel", "panel-simple";
            backlight = <&backlight>;
            status = "okay";
    
            port {
                panel_input: endpoint {
                    remote-endpoint = <&oldi0_output>;
                };
            };
        };
            backlight: ecap1-backlight {
            compatible = "pwm-backlight";
            pwms = <&ecap1 0 1000000 0>;
            brightness-levels = <0 64 128 192 255>;
            default-brightness-level = <4>;
            pinctrl-names = "default";
            pinctrl-0 = <&pinctrl_backlight>;
            status = "okay";
        };
        &oldi0 {
        status = "okay";
    };
    
    &oldi0_ports {
        #address-cells = <1>;
        #size-cells = <0>;
    
        // DSS → OLDI0
        port@0 {
            reg = <0>;
            oldi0_input: endpoint {
                remote-endpoint = <&dss_to_oldi>;
            };
        };
    
        // OLDI0 → Panel
        port@1 {
            reg = <1>;
            oldi0_output: endpoint {
                remote-endpoint = <&panel_input>;
            };
        };
    };
    
    &dss_ports {
        #address-cells = <1>;
        #size-cells = <0>;
    
        /* port@0: OLDI output */
        port@0 {
            reg = <0>;
            dss_to_oldi: endpoint {
                remote-endpoint = <&oldi0_input>;
            };
        };
    };
    
    &ecap1 {
        status = "okay";
    };
    

  • What is the register value at 0x3020A160 ?

  • root@am62xx-evm:~# devmem2 0x3020a160
    /dev/mem opened.
    Memory mapped at address 0xffff8b25e000.
    Read at address 0x3020A160 (0xffff8b25e160): 0x00001185

  • As an experiment to solve this issue, can you please try disabling splash in u-boot.
    You can find the instructions here: https://software-dl.ti.com/processor-sdk-linux/esd/AM62X/latest/exports/docs/linux/Foundational_Components/U-Boot/UG-Splash-Screen.html#disabling-splash-screen 

  • Also, are you working with the latest SDK?

  • Before changing, there were fb0 and fb1, and fb1 was connected to the panel.

    I changed the u-boot configuration.

    CONFIG_VIDEO=n
    CONFIG_SYS_WHITE_ON_BLACK=n
    CONFIG_SPL_VIDEO_TIDSS=n
    CONFIG_VIDEO_BMP_GZIP=n
    CONFIG_BMP=n
    CONFIG_BMP_24BPP=n
    CONFIG_BMP_32BPP=n
    CONFIG_SPL_VIDEO=n
    CONFIG_SPL_SPLASH_SCREEN=n
    CONFIG_SPL_SYS_WHITE_ON_BLACK=n
    CONFIG_SPL_SPLASH_SCREEN_ALIGN=n
    CONFIG_SPL_SPLASH_SOURCE=n
    CONFIG_SPL_VIDEO_BMP_GZIP=n
    CONFIG_SPL_BMP_24BPP=n
    CONFIG_SPL_BMP_32BPP=n
    CONFIG_SPL_HIDE_LOGO_VERSION=n
    CONFIG_CMD_BMP=n
    CONFIG_SPL_BMP=n
    CONFIG_FDT_SIMPLEFB=n

    I buit tisdk-default-image, and copied tiboot3.bin, tispl.bin, and u-boot.img to SD card.

    After changing, fb1 was removed, and fb0 was connected to the panel.

    But, after changing, nothing is displayed on the panel when filling fb0 with 0x00FFFF00 manually.

  • What do the following commands return?
    kmsprint
    modetest -M tidss
    kmstest

    ?

  • root@am62xx-evm:~# kmsprint
    Connector 0 (40) LVDS-1 (connected)
      Encoder 0 (39) NONE
        Crtc 0 (38) 800x480@59.08 25.000 800/8/4/8/? 480/16/4/16/? 59 (59.08) 0x0 0x48
          Plane 0 (31) fb-id: 48 (crtcs: 0) 0,0 800x480 -> 0,0 800x480 (AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12)
            FB 48 800x480
    root@am62xx-evm:~# modetest -M tidss
    Encoders:
    id      crtc    type    possible crtcs  possible clones
    39      38      none    0x00000001      0x00000001
    
    Connectors:
    id      encoder status          name            size (mm)       modes   encoders
    40      39      connected       LVDS-1          95x55           1       39
      modes:
            index name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot
      #0 800x480 59.08 800 808 812 820 480 496 500 516 25000 flags: ; type: preferred, driver
      props:
            1 EDID:
                    flags: immutable blob
                    blobs:
    
                    value:
            2 DPMS:
                    flags: enum
                    enums: On=0 Standby=1 Suspend=2 Off=3
                    value: 0
            5 link-status:
                    flags: enum
                    enums: Good=0 Bad=1
                    value: 0
            6 non-desktop:
                    flags: immutable range
                    values: 0 1
                    value: 0
            4 TILE:
                    flags: immutable blob
                    blobs:
    
                    value:
    
    CRTCs:
    id      fb      pos     size
    38      48      (0,0)   (800x480)
      #0 800x480 59.08 800 808 812 820 480 496 500 516 25000 flags: ; type: preferred, driver
      props:
            24 VRR_ENABLED:
                    flags: range
                    values: 0 1
                    value: 0
            27 CTM:
                    flags: blob
                    blobs:
    
                    value:
            28 GAMMA_LUT:
                    flags: blob
                    blobs:
    
                    value:
            29 GAMMA_LUT_SIZE:
                    flags: immutable range
                    values: 0 4294967295
                    value: 256
    
    Planes:
    id      crtc    fb      CRTC x,y        x,y     gamma size      possible crtcs
    31      38      48      0,0             0,0     0               0x00000001
      formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
      props:
            8 type:
                    flags: immutable enum
                    enums: Overlay=0 Primary=1 Cursor=2
                    value: 1
            30 IN_FORMATS:
                    flags: immutable blob
                    blobs:
    
                    value:
                            01000000000000001d00000018000000
                            01000000900000004152313241423132
                            52413132524731364247313641523135
                            41423135415232344142323452413234
                            42413234524732344247323441523330
                            41423330585231325842313252583132
                            58523135584231355852323458423234
                            52583234425832345852333058423330
                            59555956555956594e56313200000000
                            ffffff1f000000000000000000000000
                            0000000000000000
                    in_formats blob decoded:
                             AR12:  LINEAR(0x0)
                             AB12:  LINEAR(0x0)
                             RA12:  LINEAR(0x0)
                             RG16:  LINEAR(0x0)
                             BG16:  LINEAR(0x0)
                             AR15:  LINEAR(0x0)
                             AB15:  LINEAR(0x0)
                             AR24:  LINEAR(0x0)
                             AB24:  LINEAR(0x0)
                             RA24:  LINEAR(0x0)
                             BA24:  LINEAR(0x0)
                             RG24:  LINEAR(0x0)
                             BG24:  LINEAR(0x0)
                             AR30:  LINEAR(0x0)
                             AB30:  LINEAR(0x0)
                             XR12:  LINEAR(0x0)
                             XB12:  LINEAR(0x0)
                             RX12:  LINEAR(0x0)
                             XR15:  LINEAR(0x0)
                             XB15:  LINEAR(0x0)
                             XR24:  LINEAR(0x0)
                             XB24:  LINEAR(0x0)
                             RX24:  LINEAR(0x0)
                             BX24:  LINEAR(0x0)
                             XR30:  LINEAR(0x0)
                             XB30:  LINEAR(0x0)
                             YUYV:  LINEAR(0x0)
                             UYVY:  LINEAR(0x0)
                             NV12:  LINEAR(0x0)
            33 zpos:
                    flags: range
                    values: 0 1
                    value: 0
            34 COLOR_ENCODING:
                    flags: enum
                    enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                    value: 0
            35 COLOR_RANGE:
                    flags: enum
                    enums: YCbCr limited range=0 YCbCr full range=1
                    value: 1
            36 alpha:
                    flags: range
                    values: 0 65535
                    value: 65535
            37 pixel blend mode:
                    flags: enum
                    enums: Pre-multiplied=0 Coverage=1
                    value: 0
    41      0       0       0,0             0,0     0               0x00000001
      formats: AR12 AB12 RA12 RG16 BG16 AR15 AB15 AR24 AB24 RA24 BA24 RG24 BG24 AR30 AB30 XR12 XB12 RX12 XR15 XB15 XR24 XB24 RX24 BX24 XR30 XB30 YUYV UYVY NV12
      props:
            8 type:
                    flags: immutable enum
                    enums: Overlay=0 Primary=1 Cursor=2
                    value: 0
            30 IN_FORMATS:
                    flags: immutable blob
                    blobs:
    
                    value:
                            01000000000000001d00000018000000
                            01000000900000004152313241423132
                            52413132524731364247313641523135
                            41423135415232344142323452413234
                            42413234524732344247323441523330
                            41423330585231325842313252583132
                            58523135584231355852323458423234
                            52583234425832345852333058423330
                            59555956555956594e56313200000000
                            ffffff1f000000000000000000000000
                            0000000000000000
                    in_formats blob decoded:
                             AR12:  LINEAR(0x0)
                             AB12:  LINEAR(0x0)
                             RA12:  LINEAR(0x0)
                             RG16:  LINEAR(0x0)
                             BG16:  LINEAR(0x0)
                             AR15:  LINEAR(0x0)
                             AB15:  LINEAR(0x0)
                             AR24:  LINEAR(0x0)
                             AB24:  LINEAR(0x0)
                             RA24:  LINEAR(0x0)
                             BA24:  LINEAR(0x0)
                             RG24:  LINEAR(0x0)
                             BG24:  LINEAR(0x0)
                             AR30:  LINEAR(0x0)
                             AB30:  LINEAR(0x0)
                             XR12:  LINEAR(0x0)
                             XB12:  LINEAR(0x0)
                             RX12:  LINEAR(0x0)
                             XR15:  LINEAR(0x0)
                             XB15:  LINEAR(0x0)
                             XR24:  LINEAR(0x0)
                             XB24:  LINEAR(0x0)
                             RX24:  LINEAR(0x0)
                             BX24:  LINEAR(0x0)
                             XR30:  LINEAR(0x0)
                             XB30:  LINEAR(0x0)
                             YUYV:  LINEAR(0x0)
                             UYVY:  LINEAR(0x0)
                             NV12:  LINEAR(0x0)
            43 zpos:
                    flags: range
                    values: 0 1
                    value: 1
            44 COLOR_ENCODING:
                    flags: enum
                    enums: ITU-R BT.601 YCbCr=0 ITU-R BT.709 YCbCr=1
                    value: 0
            45 COLOR_RANGE:
                    flags: enum
                    enums: YCbCr limited range=0 YCbCr full range=1
                    value: 1
            46 alpha:
                    flags: range
                    values: 0 65535
                    value: 65535
            47 pixel blend mode:
                    flags: enum
                    enums: Pre-multiplied=0 Coverage=1
                    value: 0
    
    Frame buffers:
    id      size    pitch
    
    root@am62xx-evm:~# kmstest
    Connector 0/@40: LVDS-1
      Crtc 0/@38: 800x480@59.08 25.000 800/8/4/8/? 480/16/4/16/? 59 (59.08) 0x0 0x48
      Plane 0/@31: 0,0-800x480
        Fb 49 800x480-XR24
    press enter to exit

  • What do you see on screen with kmstest?

  • Nothing is seen, but black screen.

  • There was a similar issue seen before: RE: AM625-Q1: Single channel OLDI output : only half display screen 
    There also a SL JEIDA LVDS panel was being used.

    1. Your panel is not getting configured in JEIDA mode . 0x3020A160 should have value 0x1183 instead of 0x1185. Can you try defining dts in similar way? Are you sure your panel uses JEIDA format and not VESA?
    2. Their resolution came from modifying U-Boot dts as similar to kernel dts. But having no display with on disabling splash doesn't really make sense, specially since linux throws no errors.
    3. Can you confirm the SDK version you are using. You shared link for 10.1, and latest is 11.1. If not using latest, can you try with latest SDK?
      

  • 1. When I revert to panel-lvds, 0x3020A160 is 0x1183. I think there was misconfiguration while transforming panel-lvds to panel-simple.

    3. I am using 10.1. I have to ask my customer if I can use 11.1. They picked 10.1 version.

  • 1. When using panel-simple, what happens when you force set that register to 0x1183 using:
    devmem2 0x3020a160  w 0x1183 ?
    2. Probably beneficial if you check 11.1 SDK is able to resolve that issue before you ask your customer if they can migrate.

  • 1. Still, nothing is on the screen when 0x3020a160 is 0x1183 and splash is disabled in u-boot. I modified dts for 0x3020a160 to be 0x1183.

  • Can you try the following:
    re-enable splash
    Use the following patch in U-Boot: /cfs-file/__key/communityserver-discussions-components-files/791/0003_2D00_lvds.patch

    N
    ote this patch was used by someone in E2E community to resolve similar issue, but this patch applies on U-Boot 2023 and not 2025.
    Start by replacing `panel_lvds: panel-lvds {` by `display {` and see what happens?

  • The structure of the patch is directly connected from dss to panel. However, our structure is designed to go from dss to oldi and then to panel. Isn't the process of going through oldi necessary?

    Patch: oldi_out0(dss port0) -> lcd_in0(panel)

    My Code: dss_to_oldi(dss port0) -> oldi0_input(oldi0 port0) -> oldi0_output(oldi0 port1) -> panel_input(panel)

  • Keeping an OLDI bridge is good for abstraction purposes, though that bridge does not need a driver being configured in Linux.
    Since the cause of this issue is still unknown and we cannot replicate you setup on our end, I would recommend trying this once.

  • When changed the device tree according to the patch, the LCD doesn't turn on.

  • Does doubling hdisplay, and doubling the clock without changing any other timing parameter show full screen?

  • When clock is doubled, the image is displayed only on the left side of the LCD, but it flickers.

    When hdisplay is doubled, the entire screen becomes white, regardless of the original image.

    When clock and hdisplay are doubled, the entire screen is blank.

  • Thanks. The fact that disabling U-Boot, Linux is not able to run the panel at all (you saw blank screen) suggests that here is something wrong your timing parameters. I'd suggest you check those with your panel vendor. You may also probe the output clock frequency to cross check, but I do not see any other issue with the setup.