TDA4VH-Q1: After the model was exported, there was an abnormal crash issue on the EVM.

Hi;

Thanks for the question. 

I did  not see the attached file. Could you uploaded them again?

Also, please share the exact commands/steps that you have used on EVM, and on PC simulation. We will try to replicate them on our side.

regards

Wen Li 

Hi; 

Also, I just want to firm that you are using this "https://www.ti.com/tool/J784S4XEVM" board. So we will have the same hardware setup as you have too.

Thanks!

Wen Li 

Hi Wenli

For the attachment, please check https://tidrive.ext.ti.com/a/LF5HNu7eR3s-Xkcu/0cf65a13-1543-471e-b4f5-f8271d9bef1e?l The file is too large for e2e.

Wen Li said:

I just want to firm that you are using this "">www.ti.com/.../quote]

We can confirm this.

Regards,

Adam

Yes, we are using TDA4VH. Our version of TIDL is 11_00_08.

Adam asked me to upload it to this link: https://tidrive.ext.ti.com/u/rhCtoWyQreu8EK25/be82eaa2-15a4-499e-86cf-b0b09afca3a1?l     密码是：7_JuHpD2

Thanks Hongyao and Adam; I got the files. And I will have the EVM board available tomorrow morning and will try to test it.

Best regards

Wen Li

Hi;

I have tried to run your .out file, I copy the EVM_test directory to the target. And run the same command in your screenshot. It indicated some library is missing. Please see the screen-shot.

I will try the other way to run it. 

Regards

Wen Li 

Thank you for your support. We hope to test the 16-bit model export configuration first.

Hello;

I have loaded your "hirain_tidl_inference_app_16bit.out" to the EVM, I got the same error message, saying "shared libraries: libtiovx_common.so" is missing.

At this point, we would like to start on PC side first. To make sure TI-OpenVX and TI-SDK is working properly.  Could you provide how your RTOS-SDK and libtiovx had been built?

Best regards

Wen Li

Hi;

Also; by looking at your model import setting file and input data files. The jpeg images have been used as input, which are fine for the simulation on PC simulation. But the jpeg will not work on the EVM. So we recommend to convert all the jpeg images to .bmp format, this is the format will work on the EVM.

Best regards

Wen Li

Hello;

Based on your model import file "tidl_config.txt", I did some modifications, now I can compile your model with a .bmp file as a data input. 

But after talking to my co-worker, she think that your problem may be resolved after the patch release 

11.01.04.01

So please check it out first. 

Also, below is my model import file so far.

=================

modelType = 2
numParamBits = 16
numFeatureBits = 16
quantizationStyle = 3
inputNetFile = "/home/wen/E2E_cases/HiRain/model_test/Model/onnx/SimpleBev_OD.onnx"
outputNetFile = "/home/wen/E2E_cases/HiRain/my_test/output/tidl_net.bin"
outputParamsFile = "/home/wen/E2E_cases/HiRain/my_test/output/tidl_io_"
inDataNorm = 0 0 0 0 0 0 0 0
inMean = 123.675 116.28 103.53
inScale = 0.01712 0.01750 0.01743
inDataFormat = 1
foldPreBnConv2D = 0 0 0 0 0 0 0 0
rawDataInElementType = 0 0 0 0 0 0 3 1
inElementType = 0 0 0 0 0 0 3 1
inWidth = 768 768 768 768 768 768 2 32768
inHeight = 576 576 576 576 576 576 32768 64
inNumChannels = 3 3 3 3 3 3 6 1
numBatches = 1 1 1 1 1 1 1 1
numFrames = 1 1 1 1 1 1 1 1
inQuantFactor = 1.0 1.0 1.0 1.0 1.0 1.0 16384.0 64.0

#inData = "/home/wen/All_SDK/J784S4/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/ti_dl/test/testvecs/input/HiRain/input_data.txt"
inData = "/home/wen/All_SDK/J784S4/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/ti_dl/test/testvecs/input/HiRain/airshow.bmp"
inFileFormat = 0

inDataNamesList = "image_svc_left, image_svc_front, image_svc_right, image_svc_rear, image_front_wide, image_rear, ref_2d, bev_mask_all"
outDataNamesList = "mono_box_cls, mono_box_pred_3d"

#outputFeature16bitNamesList = "/svc_od_head/hm/hm.1/Conv_output_0_12"
#params16bitNamesList = "/svc_od_head/hm/hm.1/Conv_output_0_12"

perfSimConfig = "/home/wen/All_SDK/J784S4/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/ti_dl/test/testvecs/config/import/device_config.cfg"

tidlStatsTool = "/home/wen/All_SDK/J784S4/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/tidl_tools/PC_dsp_test_dl_algo.out"
perfSimTool = "/home/wen/All_SDK/J784S4/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/tidl_tools/ti_cnnperfsim.out"
graphVizTool = "/home/wen/All_SDK/J784S4/ti-processor-sdk-rtos-j784s4-evm-11_00_00_06/c7x-mma-tidl/tidl_tools/tidl_graphVisualiser.out"

debugTraceLevel = 1
writeTraceLevel = 1
writeOutput = 2
postProcType = 0
compileConstraintsFlag = 83886080

Best regards

Wen Li