AM620-Q1: Synchronization of McASP instances

Hi Wojciech,

There was a similar frame sync alignment implementation that was made for AM273 board and 2 McASP instances. The theoretical process will look somewhat like - 

Step 1: Peripheral Configuration
The system is initialized by configuring the necessary hardware modules:

• McASP1 (Reference): Configured to transmit a TDM stream with a 48kHz FSYNC rate. This serves as the timing reference.

• McASP2 (Target): Configured to transmit a TDM stream with a 48kHz FSYNC rate. This is the output to be adjusted.

• eCAP1 (Reference Monitor): Set to capture the timestamp of each rising edge of the McASP1 FSYNC and to trigger an ISR upon this event.

• eCAP2 (Target Monitor): Set to capture the timestamp of each rising edge of the McASP2 FSYNC.

  [eCAP (Enhanced Capture Module) is a A high-precision timer peripheral used for capturing event timestamps, such as the rising edge of an FSYNC signal.]

Step 2: Event Capture and Measurement
Upon the arrival of the 48kHz FSYNC from McASP1, the following occurs autonomously:

1. eCAP1 captures the McASP1 FSYNC timestamp.

2. The configured interrupt is asserted, triggering the execution of the ISR.

3. eCAP2 captures the McASP2 FSYNC timestamp.

Step 3: Phase Error Calculation and Evaluation
Inside the ISR, the processor performs the following calculations:

1. Read Timestamps: The timestamp values from eCAP1 and eCAP2 registers are read.

2. Calculate Phase Error (Δt): The phase deviation is calculated as Δt = timestamp(eCAP2) - timestamp(eCAP1).

3. Evaluate Tolerance: The absolute value of the phase error, |Δt|, is compared against a pre-defined tolerance threshold.

Step 4: Phase Correction
Based on the evaluation, a decision is made:

• If Within Tolerance: The system is considered synchronized. The ISR exits with no corrective action.

• If Outside Tolerance: A phase correction is required. The ISR initiates a "clock nudge" on the BCLK of McASP2. This controlled, single-cycle delay realigns the McASP2 FSYNC pulse with the McASP1 reference, reducing the phase error in the next cycle.

The below image shows how this is done. [ This is just for reference. But can be used for understanding purpose ]

Regards,
Ritapravo