Tool/software:
Hi，
Because if configured as GEN3 during startup, there is a probability that the external Switch chip cannot be recognized, resulting in driver loading failure. Therefore, GEN2 is defaulted during startup. Is there a way to modify the PCIE rate from GEN2 to GEN3 after TDA4 startup?
Regards，
Yang
Hi，
I have checked the register instructions and it seems to be set as an EP node. I am currently using the PCIE3 RP function. Which registers should I set?
Regards，
Yang
Hi，
We are currently using Linux, and I have tried the command you sent. It can modify PCIE Speed to GEN3, but sometimes it takes multiple executions to
succeed. Why is that?
The following figure shows the default properties after power on:
The following is the log that I have made multiple modifications to:
Regards，
Yang
Hi，
Due to current functional limitations, I must keep PCIE at GEN2 during startup. Therefore, I manually set PCIE to GEN2 in the code, which results in Lnkcap
being only 5GT/s during system startup. Is there any way to modify this property?
Regards，
Yang
Hi,
I tried on AM69 just now as an experiment to see if I can retrain link to a speed greater than advertised in lnkcap register. Seems to link up to 8GT/s on first try. The issue might be somewhere else then.
It may be an equalization phase issue during the retraining. Can you check the LnkSta2 register in PCIe config space that says whether certain equalization phases passed.
Also, a lot of PCIe problems stem from clock issues, since both the root port and endpoint need to be properly synced to avoid issues.
What is the clock configuration, refclk?
What is the source for both J7 and the PCIe endpoint?
Do they have a shared clock?
Is it an external clock, or configured by J7 internally by its PLL?
Regards,
Jeff
Hi，
The following is information about LnkSta2:
What is the clock configuration, refclk?
Yes, the current refclk is the default refclk inside the TDA4.
What is the source for both J7 and the PCIe endpoint?
EP is a MVL switch.
Do they have a shared clock?
Is it an external clock, or configured by J7 internally by its PLL?
The clock configured by the PLL inside the J7.
Regards，
Yang
Hi,
Hmmm, it appears that the link equalization failed or possibly never even started. The link must be in state L0 when equalization begins. Are you familiar with reading the TI registers of the PCIe controller? If so, there is a register that holds the value of the state the LTSSM is in. I am curious to know if the link is in the proper state of L0 when equalization begins. If you can find the controller base address, the LTSSM register offset is located in bits 29:24 of that register. That will tell you the state of the link. Can you read that register/memory after you set the new speed but before you set the retraining bit?
Regards,
Jeff
Hi，
From the figure below, it can be seen that after setting the new speed, the register values did not change, but the register low bits changed after retraining.
The following figure shows that the register value remains unchanged even when the speed modification fails.
Regards，
Yang
Hi,
If you could poll it every ~1ms, that would be a good place to start. a 5ms interval might be acceptable. You will enter different Recovery states as it progresses through link equalization. Also, continue to check LnkSta2 because it will show which stages of equalization were successfully completed (if any).
Below is a table from our TRM that shows the different states and the value that represents them in the register bitfield.
Regards,
Jeff
