DRA821U: QSPI flash operating clock on DRA821U

Rich Chen

Expert 4180 points

Part Number: DRA821U
Other Parts Discussed in Thread: DRA821, TDA4VH, DRA829, DA8XX

Tool/software:

Champ,

Customer feedback QSPI Flash on J7200 EVM will switch back to 1 bit mode if clock set over 25Mhz.

Customer found the QSPI flash boot time is slow then check SDK default QSPI clock setting is 25Mhz.

Customer try to set it to 40Mhz to reduce booting time but found it getting slower.

Then they use oscilloscope to measure the waveform and found it will turn back to 1 bit mode while original operating in Quad bit mode.

Is it possible to increase QSPI clock but still stay in quad bit mode? AM62x and AM64x has no such limitation in SDK.

BR, Rich

2 months ago

0 Tanmay Patil 2 months ago

TI__Mastermind 39040 points

Hi,

The output clock of QSPI should be limited to 25MHz even in AM62x and AM64x.

To increase the rate further, you should use OSPI in phy mode. This can go upto 166MHz

Regards,
Tanmay

0 Rich Chen 2 months ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

Do you mean customer need to switch to PHY mode if they want to increase clock speed?

25Mhz is the maximum recommend clock without using PHY mode.

BR, Rich

0 Tanmay Patil 2 months ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi,

Yes that is correct.

Regards,
Tanmay

0 Rich Chen 1 month ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

Customer would like to know how to enable PHY mode and switch to a higher clock rate said 40Mhz?

Below are the changes they made but QSPI access will crash after changing.

Could you check whether the setting is correct and what is missing?

Uboot:

iff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi

index 910a4b5c..d51b219f 100644

--- a/arch/arm/dts/k3-j7200-som-p0.dtsi

+++ b/arch/arm/dts/k3-j7200-som-p0.dtsi

@@ -427,14 +427,17 @@

flash@0 {

compatible = "jedec,spi-nor";

reg = <0x0>;

- spi-tx-bus-width = <8>;

- spi-rx-bus-width = <8>;

+ spi-tx-bus-width = <4>;

+ spi-rx-bus-width = <4>;

- spi-max-frequency = <25000000>;

- cdns,tshsl-ns = <60>;

- cdns,tsd2d-ns = <60>;

- cdns,tchsh-ns = <60>;

- cdns,tslch-ns = <60>;

+ cdns,phy-mode;

Kernel:

diff --git a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

index 81bb0d656..e27e0b9c2 100644

--- a/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

+++ b/arch/arm64/boot/dts/ti/k3-j7200-som-p0.dtsi

@@ -284,7 +284,7 @@

reg = <0x0>;

spi-tx-bus-width = <8>;

spi-rx-bus-width = <8>;

- spi-max-frequency = <25000000>;

+ spi-max-frequency = <40000000>;

cdns,tshsl-ns = <60>;

cdns,tsd2d-ns = <60>;

cdns,tchsh-ns = <60>;

BR, Rich

0 Tanmay Patil 1 month ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

The u-boot and kernel are exclusive. Are you testing the changes with u-boot or kernel?

Regards,
Tanmay

0 Rich Chen 1 month ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

Customer test both u-boot and Kernel and the goal is to increase booting time so u-boot is targeted as priority.

Customer claim enable PHY mode and increase clock to 40Mhz will fail the QSPI access.

He wants to verify this on DRA821 EVM with OSPI flash running at 40Mhz.

Could you try this on DRA821 EVM and provide a patch to customer to verify on EVM and port onto their own board?

BR, Rich

0 Rich Chen 1 month ago in reply to Rich Chen

TI__Expert 4180 points

Tanmay,

Is this feasible to support on DRA821 EVM?

It should be supported and verifying on EVM is the easiest path to go before debugging on customer target board.

BR, Rich

0 Tanmay Patil 1 month ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

phy mode cannot be used in QSPI mode. It can only be done with OSPI flashes.

Regards,
Tanmay

0 Rich Chen 1 month ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

Then how to increase QSPI clock up to 40MHz? The goal is to increase QSPI NOR flash booting speed to reduce booting time.

Is this achievable?

If the answer is Yes, how to do it?

BR, Rich

0 Tanmay Patil 1 month ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

This might not be even possible. I am checking with our hardware expert what exactly is the limit here. But with QSPI, we haven't gone beyond 25MHz.

Regards,
Tanmay

0 Rich Chen 1 month ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

Please do confirm this with validation team.

I checked into DRA821 Data Manual, for OSPI without Data Training in DDR mode, the min clock cycle is 19ns which is close to 50Mhz. For SDR mode, the min clock cycle is 7ns and 7.52ns which is at least 133Mhz.

With Data Training, DDR mode 1.8V can achieve 166Mhz and 3.3V can achieve 133Mhz.

I would like to confirm whether Data Training is equal to PHY mode you mentioned in this post?

There is no such limitation on AM62x and AM64x and I wonder if this is a hardware limitation or software configuration limitation probably from PLL clock.

May you contact our OSPI flash driver developer to double confirm this?

BR, Rich

0 Tanmay Patil 1 month ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

Rich Chen said:
I would like to confirm whether Data Training is equal to PHY mode you mentioned in this post?

Yes. Data training is the phy mode I mentioned before.

Regards,
Tanmay

0 Rich Chen 1 month ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

In this case, the OSPI/QSPI could achieve ~50Mhz even without PHY mode (No Data trained).

This should not be a limitation to OSPI/QSPI flash. (In fact, we don't have this limitation on our other platforms including TDA4.)

Please help to make 40Mhz clock work on EVM QSPI flash and provide a patch on how to enable the support. (no matter PHY mode or non PHY mode)

BR, Rich

0 kcastille 1 month ago in reply to Rich Chen

TI__Guru 54512 points

Rich, Tanmay.

Are you targeting DDR or SDR mode? SDR should be able to run up to 50 MHz in TAP (no PHY) mode. DDR is limited to 25 MHz.

The DRA821 datasheet is slightly outdated. You can refer to TDA4VH as a rough template for what can be supported/

Regards,

Kyle

0 Rich Chen 1 month ago in reply to kcastille

TI__Expert 4180 points

Kyle,

Thanks for the confirmation.

SDR 50Mhz can achieve about 25Mhz throughtput theoretically.

In this case, if original QSPI is using DDR already, then there is no way to reduce booting time by change to SDR 40 or even 50Mhz.

That’s to say the only choice will be using PHY mode to support DDR over 25MHz.

Tanmay,

Could you confirm whether current QSPI driver is actual DDR already?

If it is DDR already, the we need an example/patch to enable PHY mode support in 40 or 50MHz DDR for the QSPI flash on EVM.

Do we have PHY mode support example already we can share?

BR, Rich

0 Tanmay Patil 1 month ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

Rich Chen said:
Could you confirm whether current QSPI driver is actual DDR already?

If it is DDR already, the we need an example/patch to enable PHY mode support in 40 or 50MHz DDR for the QSPI flash on EVM.

Do we have PHY mode support example already we can share?

i will confirm this by end of day.

Regards,
Tanmay

0 Tanmay Patil 1 month ago in reply to Tanmay Patil

TI__Mastermind 39040 points

Hi Rich,

The QSPI driver is SDR only. We have never tried to make it DDR or take it to Phy mode. I do believe that is possible, but lets wait for a confirmation from Kyle for this. But as we have never tried this on EVM, I don't know what kind of issues we might see with this.

But before this, Have we made sure that the QSPI flash being used also has those capabilities? Is it possible to share the part number here?

Regards,
Tanmay

0 Rich Chen 1 month ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

I checked the QSPI flash MT25QU512ABB8E12-0AUT part detail on DRA821 EVM which supports SDR and DTR(DDR) both.

Customer board use MX25L25645G supports SDR and DTR(DDR) both.

1. If current QSPI driver is SDR only, it should be capable to operate at 40Mhz or even 50Mhz SDR mode according to specification.

2. We need to enable DTR support in QSPI for 25Mhz.

Could you contact our OSPI driver developer to enable this?

BR, Rich

0 Rich Chen 29 days ago in reply to Rich Chen

TI__Expert 4180 points

Tanmay,

Is team working on enabling 40Mhz SDK support for QSPI flash or DTR support for 25Mhz on EVM now?

Do we have a timeline to get a patch enabling it?

BR, Rich

0 Rich Chen 26 days ago in reply to Rich Chen

TI__Expert 4180 points

Tanmay,

Could you update current finding and plan on this request?

Have you got driver developer feedback?

BR, Rich

0 Bo Mellberg 18 days ago in reply to Rich Chen

Intellectual 581 points

Hi experts,

Sorry to hi-jack the thread but I am also very interested in getting the speed up on QSPI (on ospi1).

Using spi-tx-bus-width = <4> in U-Boot, I have never gotten any stability. I can write to the nor flash but the following reads shows garbled bytes.

Can you confirm that using quad lines on both tx and rx works in both U-Boot and Kernel? If yes, what are the dts-settings and what is the highest speed we can achieve?

Also, regarding phy-mode, there is a commit, 11 months old:

Where cdns,phy-mode is added to ospi1, which is used for qspi-nor. Is this an error?

Regards,

/Bo

0 Rich Chen 17 days ago in reply to Bo Mellberg

TI__Expert 4180 points

Tanmay,

Are you working on this ticket? There are also other customers need to get assistant from team.

Can we increase the clock speed over 25Mhz for QSPI NOR? Said 40Mhz.

Is current a software limitation or not implemented? What's the plan to enable this?

BR, Rich

0 Tanmay Patil 16 days ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi,

I can see from the DRA829 EVM that I am able to set the QSPI speed to 40MHz in SDR mode (unable to test this on DRA821 evm as it does not have a QSPI flash). The nodes used for this are as follows:

In k3-j721e-common-proc-board.dts:

&ospi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "qspi.tiboot3";
				reg = <0x0 0x80000>;
			};

			partition@80000 {
				label = "qspi.tispl";
				reg = <0x80000 0x200000>;
			};

			partition@280000 {
				label = "qspi.u-boot";
				reg = <0x280000 0x400000>;
			};

			partition@680000 {
				label = "qspi.env";
				reg = <0x680000 0x20000>;
			};

			partition@6a0000 {
				label = "qspi.env.backup";
				reg = <0x6a0000 0x20000>;
			};

			partition@6c0000 {
				label = "qspi.sysfw";
				reg = <0x6c0000 0x100000>;
			};

			partition@800000 {
				label = "qspi.rootfs";
				reg = <0x800000 0x37c0000>;
			};

			partition@3fe0000 {
				label = "qspi.phypattern";
				reg = <0x3fe0000 0x20000>;
			};
		};
	};
};

In k3-j721e-mcu-wakeup.dtsi:

		ospi1: spi@47050000 {
			compatible = "ti,am654-ospi", "cdns,qspi-nor";
			reg = <0x0 0x47050000 0x0 0x100>,
				<0x7 0x00000000 0x1 0x00000000>;
			interrupts = <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>;
			cdns,fifo-depth = <256>;
			cdns,fifo-width = <4>;
			cdns,trigger-address = <0x0>;
			cdns,phase-detect-selector = <2>;
			clocks = <&k3_clks 104 0>;
			power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
			#address-cells = <1>;
			#size-cells = <0>;
			status = "disabled";
		};

Can you try to match this configuration and see the results on customer board?

Can you also apply this patch to get more debug prints in u-boot for qspi :

diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index 0448b9929ca..6ffdacafaa8 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -29,6 +29,8 @@
 #define CQSPI_READ                     2
 #define CQSPI_WRITE                    3

+#define _DEBUG 1
+
 __weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
                                     const struct spi_mem_op *op)
 {
@@ -1243,6 +1245,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
                               priv->tshsl_ns, priv->tsd2d_ns,
                               priv->tchsh_ns, priv->tslch_ns);

+       debug("%s: speed=%d\n", __func__, hz);
+
        return 0;
 }

Bo Mellberg said:
Using spi-tx-bus-width = <4> in U-Boot, I have never gotten any stability. I can write to the nor flash but the following reads shows garbled bytes.

Is there any specific reason to use 4 lines for write speed? By deault in SDK we have 1 for write and 4 for tx.

Regards,
Tanmay

0 Alvin Chen 16 days ago in reply to Tanmay Patil

Intellectual 510 points

U-Boot SPL 2024.04-g86f9bd3c-dirty (Sep 18 2025 - 14:53:59 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Trying to boot from SPI
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=500000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
cadence_spi_write_speed: speed=25000000
cadence_spi_set_speed: speed=25000000
SPL: replica=0
SPL: Normal mode..
Authentication passed
Authentication passed

U-Boot 2024.04-g86f9bd3c-dirty (Sep 18 2025 - 14:53:59 +0800)

U-Boot SPL 2024.04-g86f9bd3c-dirty (Sep 18 2025 - 14:52:10 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')

DDR type: Micron LPDDR4 4G

Trying to boot from SPI
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=50000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_write_speed: speed=25000000
cadence_spi_set_speed: speed=25000000
Authentication passed
Authentication passed
Authentication passed
Authentication passed
Authentication passed
Starting ATF on ARM64 core...

NOTICE: BL31: v2.10.0(release):86f9bd3c-dirty
NOTICE: BL31: Built : 14:52:36, Sep 18 2025
I/TC:
I/TC: OP-TEE version: 86f9bd3c-dev (gcc version 9.2.1 20191025 (GNU Toolchain for the A-profile Architecture 9.2-2019.12 (arm-9.10))) #2 Thu Sep 18 06:53:04 UTC 2025 aarch64
I/TC: WARNING: This OP-TEE configuration might be insecure!
I/TC: WARNING: Please check optee.readthedocs.io/.../porting_guidelines.html
I/TC: Primary CPU initializing
I/TC: GIC redistributor base address not provided
I/TC: Assuming default GIC group status and modifier
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Secure Board Configuration Software: Rev 1
I/TC: Secure Boot Keys: Count 2, Rev 1
I/TC: HUK Initialized
I/TC: Primary CPU switching to normal world boot

U-Boot 2024.04-g86f9bd3c-dirty (Sep 18 2025 - 14:53:59 +0800)

SoC: J7200 SR2.0 HS-SE
Model: Texas Instruments J7200 EVM
DRAM: 4 GiB
Core: 107 devices, 32 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
WDT: Started with servicing (15s timeout)
MMC: mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from SPIFlash... cadence_spi spi@47040000: Unable to find PHY pattern partition
jedec_spi_nor flash@0: Software reset enable failed: -524
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
In: serial@2800000
Out: serial@2800000
Err: serial@2800000
am65_cpsw_nuss ethernet@46000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00293904 Ports:1
am65_cpsw_nuss ethernet@c000000: K3 CPSW: nuss_ver: 0x6BA02102 cpsw_ver: 0x6BA82102 ale_ver: 0x00294104 Ports:4
Net: Address in environment is 00:90:e8:11:22:00
eth0: ethernet@46000000port@1, eth1: ethernet@c000000port@1, eth2: ethernet@c000000port@2, eth3: ethernet@c000000port@3
Date: 2000-01-01 (Saturday) Time: 0:01:13
RTC: OK
tpm@0 v2.0: VendorID 0x15d1, DeviceID 0x001d, RevisionID 0x36 [open]
jedec_spi_nor flash@0: Software reset enable failed: -524
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
jedec_spi_nor flash@0: Software reset enable failed: -524
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
SF: 1048576 bytes @ 0xc60000 Read: OK
Press <DEL> To Enter BIOS configuration Setting: 0
starting USB...
Bus usb@6000000: INFO.usb, cdns-usb3-host usb@6000000: DRD version v1 (ID: 0004024e, rev: 00000200)
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.475s, speed 2241632 B/s
Register 2000840 NbrPorts 2
Starting the controller
USB XHCI 1.00
scanning bus usb@6000000 for devices... 3 USB Device(s) found
scanning usb for storage devices... 0 Storage Device(s) found
** Bad device specification usb 0 **
Couldn't find partition usb 0:1
ERR.core, Can't set block device
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.475s, speed 2246321 B/s
switch to partitions #0, OK
mmc1 is current device
ERR.core, Failed to load 'mp_uc-8600_mil3_boot.cfg'
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.473s, speed 2255760 B/s
INFO.ethernet, am65_cpsw_nuss_port ethernet@46000000port@1: K3 CPSW: rflow_id_base: 2
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.475s, speed 2246321 B/s
ethernet@46000000port@1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
ERR.ethernet, am65_cpsw_nuss_port ethernet@46000000port@1: phy_startup failed
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.473s, speed 2251031 B/s
ERR.ethernet, am65_cpsw_nuss_port ethernet@46000000port@1: am65_cpsw_start end error
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.474s, speed 2251031 B/s
INFO.misc, k3-navss-ringacc ringacc@3c000000: Ring Accelerator probed rings:1024, gp-rings[120,200] sci-dev-id:211
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.473s, speed 2251031 B/s
INFO.misc, k3-navss-ringacc ringacc@3c000000: dma-ring-reset-quirk: disabled
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.474s, speed 2251031 B/s
INFO.ethernet, am65_cpsw_nuss_port ethernet@c000000port@1: K3 CPSW: rflow_id_base: 4
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.478s, speed 2227680 B/s
ethernet@c000000port@1 Waiting for PHY auto negotiation to complete......... TIMEOUT !
ERR.ethernet, am65_cpsw_nuss_port ethernet@c000000port@1: phy_startup failed
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.475s, speed 2246321 B/s
ERR.ethernet, am65_cpsw_nuss_port ethernet@c000000port@1: am65_cpsw_start end error
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.476s, speed 2236962 B/s
INFO.ethernet, am65_cpsw_nuss_port ethernet@c000000port@2: K3 CPSW: rflow_id_base: 4
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.476s, speed 2241632 B/s
ethernet@c000000port@2 Waiting for PHY auto negotiation to complete......... TIMEOUT !
ERR.ethernet, am65_cpsw_nuss_port ethernet@c000000port@2: phy_startup failed
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.477s, speed 2236962 B/s
ERR.ethernet, am65_cpsw_nuss_port ethernet@c000000port@2: am65_cpsw_start end error
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.476s, speed 2241632 B/s
INFO.ethernet, am65_cpsw_nuss_port ethernet@c000000port@3: K3 CPSW: rflow_id_base: 4
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.474s, speed 2246321 B/s
ethernet@c000000port@3 Waiting for PHY auto negotiation to complete......... TIMEOUT !
ERR.ethernet, am65_cpsw_nuss_port ethernet@c000000port@3: phy_startup failed
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.476s, speed 2236962 B/s
ERR.ethernet, am65_cpsw_nuss_port ethernet@c000000port@3: am65_cpsw_start end error
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.475s, speed 2241632 B/s
ping failed; host 192.168.128.180 is not alive
Boot Management : Default
Boot Order : Embedded First
Embedded Storage : eMMC
External Storage : Disabled
switch to partitions #0, OK
mmc0(part 0) is current device
replica=0
Normal mode..
ERR.core, Failed to load 'working/j7200-moxa.itb'
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
device 0 offset 0xc60000, size 0x100000
8192 bytes written, 1040384 bytes skipped in 0.473s, speed 2251031 B/s
Error: load mmc 0 91000000 working/j7200-moxa.itb (1)
Boot to Linux Fail

0 Alvin Chen 16 days ago in reply to Alvin Chen

Intellectual 510 points

HI TI

It still fail ......

0 Alvin Chen 16 days ago in reply to Alvin Chen

Intellectual 510 points

My patch

diff --git a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
index dd17d04c..54167b7f 100644
--- a/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
+++ b/arch/arm/dts/k3-j7200-common-proc-board-u-boot.dtsi
@@ -195,7 +195,6 @@
bootph-all;

flash@0 {
- cdns,phy-mode;
bootph-all;
};
};
diff --git a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
index 07f44a59..37ac2c23 100644
--- a/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm/dts/k3-j7200-mcu-wakeup.dtsi
@@ -548,16 +548,14 @@
ospi0: spi@47040000 {
compatible = "ti,am654-ospi", "cdns,qspi-nor";
reg = <0x0 0x47040000 0x0 0x100>,
- <0x5 0x00000000 0x1 0x0000000>;
+ <0x5 0x00000000 0x1 0x0000000>;
interrupts = <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>;
cdns,fifo-depth = <256>;
cdns,fifo-width = <4>;
cdns,trigger-address = <0x0>;
- clocks = <&k3_clks 103 0>;
- assigned-clocks = <&k3_clks 103 0>;
- assigned-clock-parents = <&k3_clks 103 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ cdns,phase-detect-selector = <2>;
+ clocks = <&k3_clks 104 0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
diff --git a/arch/arm/dts/k3-j7200-som-p0.dtsi b/arch/arm/dts/k3-j7200-som-p0.dtsi
index 910a4b5c..b5a7fb64 100644
--- a/arch/arm/dts/k3-j7200-som-p0.dtsi
+++ b/arch/arm/dts/k3-j7200-som-p0.dtsi
@@ -427,14 +427,14 @@
flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
- spi-tx-bus-width = <8>;
- spi-rx-bus-width = <8>;
- spi-max-frequency = <25000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <4>;
+ spi-max-frequency = <40000000>;
cdns,tshsl-ns = <60>;
cdns,tsd2d-ns = <60>;
cdns,tchsh-ns = <60>;
cdns,tslch-ns = <60>;
- cdns,read-delay = <4>;
+ cdns,read-delay = <2>;

partitions {
compatible = "fixed-partitions";
diff --git a/drivers/spi/cadence_qspi.c b/drivers/spi/cadence_qspi.c
index e0d13e36..a3b1b085 100644
--- a/drivers/spi/cadence_qspi.c
+++ b/drivers/spi/cadence_qspi.c
@@ -29,6 +29,8 @@
#define CQSPI_READ 2
#define CQSPI_WRITE 3

+#define _DEBUG 1
+
__weak int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
const struct spi_mem_op *op)
{
@@ -584,6 +586,8 @@ static int cadence_spi_write_speed(struct udevice *bus, uint hz)
priv->tshsl_ns, priv->tsd2d_ns,
priv->tchsh_ns, priv->tslch_ns);

+ debug("%s: speed=%d\n", __func__, hz);
+
return 0;
}

0 Tanmay Patil 16 days ago in reply to Alvin Chen

TI__Mastermind 39040 points

Hi,

I don't see the debug prints from the driver in the logs. Can you confirm that you are building the u-boot and copying it? I see it in a72 spl (tispl.bin), but not in u-boot.

I also see "Loading Environment from SPIFlash..." in the logs. can you share what environment is there in the flash already? What is being read? It seems that this environment has some command which runs "sf probe"

It seems that SPI boot mode is being used here. Is it possible to use some other media to get to u-boot and test flash with it?

For a debug call, I am available at 2:30 pm IST for half an hour. Let me know if that is feasible. Otherwise, we will have to tomorrow morning India time.

Regards,
Tanmay

0 Rich Chen 16 days ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay and Alvin,

From the log you posted, it looks like PHY mode is enabled.

Is my understanding correct?

Loading Environment from SPIFlash... cadence_spi spi@47040000: Unable to find PHY pattern partition

BR, Rich

0 Tanmay Patil 16 days ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

No, print comes by default because it just checks if a phy pattern partition is defined in device tree and if there exist a pattern in there.

It does not start the actual calibration for phy mode. That is not happening.

Regards,
Tanmay

0 Bo Mellberg 16 days ago in reply to Tanmay Patil

Intellectual 581 points

Is the phy calibration even expected to work?

Because in the dts:

			partition@3fe0000 {
				label = "qspi.phypattern";
				reg = <0x3fe0000 0x20000>;
			};

but in the driver:

	/*
	 * If the device tree already provides a read delay value, use that
	 * instead of calibrating.
	 */
	if (priv->read_delay >= 0) {
		cadence_spi_write_speed(bus, hz);
		cadence_qspi_apb_readdata_capture(priv->regbase, 1, true,
						  priv->read_delay);
	} else if (priv->previous_hz != hz ||
		   priv->qspi_calibrated_hz != hz ||
		   priv->qspi_calibrated_cs != spi_chip_select(bus)) {
		/*
		 * Calibration required for different current SCLK speed,
		 * requested SCLK speed or chip select
		 */
		err = spi_calibration(bus, hz);
		if (err)
			return err;

		/* prevent calibration run when same as previous request */
		priv->previous_hz = hz;
	}

So a calibration won't take place if read-delay is specified.

also in cadence_spi_ofdata_phy_pattern() function:

	while (ofnode_valid(subnode)) {
		label = ofnode_read_string(subnode, "label");
		if (label && strcmp(label, "ospi.phypattern") == 0) {
			if (!ofnode_read_u32_array(subnode, "reg", &start, 1))
				return start;
			break;
		} else if (label && strcmp(label, "ospi_nand.phypattern") == 0)
			return 0;

		subnode = ofnode_next_subnode(subnode);
	}

Which means that the partitions needs to have the exact name "ospi<.nand>.phypattern" to be found.

What is the general thought here? Avoid phy-calibration on qspi, only use 1 of 4 tx lanes and stay at 25 MHz?

Regards,

/Bo

0 Bo Mellberg 16 days ago in reply to Bo Mellberg

Intellectual 581 points

I can confirm my debug findings with Alvin:

U-Boot SPL 2024.04-ti-g8164c19ba3af (Sep 18 2025 - 08:06:28 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
Trying to boot from SPI
cadence_spi spi@47050000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47050000 ahbbase=58000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_write_speed: speed=25000000
cadence_spi_set_speed: speed=25000000
Authentication passed
Authentication passed
Authentication passed
Loading Environment from nowhere... OK
Authentication passed
Authentication passed
Starting ATF on ARM64 core...

but unlike him, I only get the above print-outs. None in later stages of booting.

/Bo

0 Tanmay Patil 16 days ago in reply to Bo Mellberg

TI__Mastermind 39040 points

Hi Rich, Bo,

Please make the following changes in the config files:

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index e23c81f84a4..743d7efedcf 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -10,7 +10,7 @@ CONFIG_SOC_K3_J721E=y
 CONFIG_TARGET_J721E_A72_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 14e9a67f3dd..21de35fc4ff 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -12,7 +12,7 @@ CONFIG_K3_QOS=y
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
-CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_SPEED=40000000
 CONFIG_ENV_SIZE=0x20000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y

This will not change the speed to 25MHz and keep it at 40MHz throughout the boot.

Bo Mellberg said:
So a calibration won't take place if read-delay is specified.

The function "spi_calibration" does not work with phy-pattern based calibration. With "spi-calibration" you can calibrate delay in TAP mode while with phy-pattern based calibration (done in "cadence_spi_mem_do_calibration()"), works with PHY mode. Both are independent modes.

The delay mentioned by "read-delay" is a fixed kind of delay for a given board (depends on schematic). Hence it is usually hardcoded. Where as the delay settings used in PHY mode have to calibrated on every time as they can vary.

In general, I believe with Jacinto devices we only have QSPI SDR mode which can run upto 40MHz.

Regards,
Tanmay

0 Rich Chen 15 days ago in reply to Tanmay Patil

TI__Expert 4180 points

Tanmay,

In this case, is it necessary to make the clock source change still?

BR, Rich

0 Alvin Chen 15 days ago in reply to Rich Chen

Intellectual 510 points

Hi Ti

I apply patch but it still back to 25000000

diff --git a/configs/j721e_evm_a72_defconfig b/configs/j721e_evm_a72_defconfig
index 789d0abd..b85c8dc8 100644
--- a/configs/j721e_evm_a72_defconfig
+++ b/configs/j721e_evm_a72_defconfig
@@ -10,7 +10,7 @@ CONFIG_SOC_K3_J721E=y
CONFIG_TARGET_J721E_A72_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
-CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
alvin@ubuntu:~/moxa_data/uboot/ti_8600_last$ git diff configs/j721e_evm_r5_defconfig
diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig
index 8d385876..4b52858d 100644
--- a/configs/j721e_evm_r5_defconfig
+++ b/configs/j721e_evm_r5_defconfig
@@ -12,7 +12,7 @@ CONFIG_K3_QOS=y
CONFIG_TARGET_J721E_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf59f0
-CONFIG_SF_DEFAULT_SPEED=25000000
+CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_ENV_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y

0 Alvin Chen 15 days ago in reply to Alvin Chen

Intellectual 510 points

U-Boot SPL 2024.04-g62074eac-dirty (Sep 19 2025 - 10:18:18 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')

DDR type: Micron LPDDR4 4G

NOTICE: BL31: v2.10.0(release):62074eac-dirty
NOTICE: BL31: Built : 10:18:42, Sep 19 2025
I/TC:
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
I/TC: Secure Board Configuration Software: Rev 1
I/TC: Secure Boot Keys: Count 2, Rev 2
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-g62074eac-dirty (Sep 19 2025 - 10:20:36 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Trying to boot from SPI
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=500000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
cadence_spi_write_speed: speed=25000000
cadence_spi_set_speed: speed=25000000
SPL: replica=0
SPL: Normal mode..
Authentication passed
Authentication passed

0 Tanmay Patil 15 days ago in reply to Alvin Chen

TI__Mastermind 39040 points

Hi,

Can you check the configs built during the build flow. In "[u-boot-dir]/build/a72/.config" and "[u-boot-dir]/build/r5/.config", you should see "CONFIG_SF_DEFAULT_SPEED=40000000". If not, you might be using the modified defconfig. can you check which defconfigs you are using and modify in them.

Note, for me, I am able to see them maintaining 40MHz with QSPI boot mode:

U-Boot SPL 2024.04-ti-dirty (Sep 18 2025 - 22:12:28 +0530)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.1.6--v10.01.06 (Fiery Fox)')
Detected: J7X-BASE-CPB rev E3
Detected: J7X-GESI-EXP rev E3
Detected: J7X-VSC8514-ETH rev E2
BOOT: WKUP_DEVSTAT=0x00000010, MAIN_DEVSTAT=0x00000000, BOOTINDEX=0
Trying to boot from SPI
In cadence_spi_ofdata_phy_pattern
cadence_spi spi@47050000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47050000 ahbbase=700000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,20] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
cadence_spi spi@47050000: Pattern not found. Skipping calibration
QSPI Debug: speed = 40000000, bus_data->speed = 40000000, mode = 0, plat->mode = 8192
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: from 0x00280000, len d
jedec_spi_nor flash@0: from 0x00280000, len d
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted

Regards,
Tanmay

0 Alvin Chen 15 days ago in reply to Alvin Chen

Intellectual 510 points

Hi Ti

Sorry , I modify wrong defconfig . Update new one.

U-Boot SPL 2024.04-g62074eac-dirty (Sep 19 2025 - 11:07:42 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')

DDR type: Micron LPDDR4 4G

Trying to boot from SPI
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=50000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
Authentication passed
Authentication passed
Authentication passed
Authentication passed
Authentication passed
Starting ATF on ARM64 core...

NOTICE: BL31: v2.10.0(release):62074eac-dirty
NOTICE: BL31: Built : 11:08:06, Sep 19 2025
I/TC:
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
I/TC: Secure Board Configuration Software: Rev 1
I/TC: Secure Boot Keys: Count 2, Rev 2
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-g62074eac-dirty (Sep 19 2025 - 11:09:32 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.0.9--v11.00.09+ (Fancy Rat)')
Trying to boot from SPI
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=500000000 max-frequency=40000000 page-size=256
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
SPL: replica=0
SPL: Normal mode..
Authentication passed
Authentication passed

U-Boot 2024.04-g62074eac-dirty (Sep 19 2025 - 11:09:32 +0800)

0 Alvin Chen 15 days ago in reply to Alvin Chen

Intellectual 510 points

configs/j7200_evm_a72_defconfig

CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x8000
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_K3_ATF_LOAD_ADDR=0x9e780000
CONFIG_TARGET_J721E_UC_8600A=y
CONFIG_TARGET_J7200_A72_EVM=y
CONFIG_ENV_SOURCE_FILE=""
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80480000
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_SIZE=0x10000
CONFIG_ENV_OFFSET=0xC00000
CONFIG_ENV_SECT_SIZE=0x10000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-common-proc-board"
CONFIG_SPL_TEXT_BASE=0x80080000
CONFIG_OF_LIBFDT_OVERLAY=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0xC20000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_PSCI_RESET is not set
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
CONFIG_BOOTSTD_FULL=y
CONFIG_BOOTDELAY=1
CONFIG_AUTOBOOT_PROMPT="Press <DEL> To Enter BIOS configuration Setting: %2d"
CONFIG_AUTOBOOT_USE_MENUKEY=y
CONFIG_AUTOBOOT_MENUKEY=127
CONFIG_OF_BOARD_SETUP=y
CONFIG_OF_SYSTEM_SETUP=y
CONFIG_LOG=y
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_BOOTCOMMAND="moxa_boot"
CONFIG_USE_PREBOOT=y
CONFIG_PREBOOT="moxa_system init"
CONFIG_DEFAULT_FDT_FILE="uc-8600a.dtb"
CONFIG_LOGLEVEL=7
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x80a00000
CONFIG_SPL_BSS_MAX_SIZE=0x80000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_SYS_MALLOC_SIMPLE=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_SYS_MALLOC_SIZE=0x800000
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1800
CONFIG_SPL_DMA=y
CONFIG_SPL_ENV_SUPPORT=y
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x700000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_WATCHDOG_SUPPORT=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_CMD_ASKENV=y
CONFIG_CMD_EEPROM=y
CONFIG_CMD_MD5SUM=y
CONFIG_CMD_MEMTEST=y
CONFIG_CMD_SHA256SUM=y
CONFIG_CMD_SHA512SUM=y
CONFIG_SHA256SUM_VERIFY=y
CONFIG_SHA512SUM_VERIFY=y
CONFIG_CMD_DFU=y
# CONFIG_CMD_FLASH is not set
CONFIG_CMD_GPIO=y
CONFIG_CMD_GPT=y
CONFIG_CMD_I2C=y
CONFIG_CMD_MMC=y
CONFIG_CMD_MMC_REG=y
CONFIG_CMD_MTD=y
CONFIG_CMD_REMOTEPROC=y
CONFIG_CMD_UFS=y
CONFIG_CMD_USB=y
CONFIG_CMD_USB_MASS_STORAGE=y
CONFIG_CMD_WDT=y
# CONFIG_BOOTP_BOOTPATH is not set
# CONFIG_BOOTP_DNS is not set
# CONFIG_BOOTP_GATEWAY is not set
# CONFIG_BOOTP_HOSTNAME is not set
# CONFIG_BOOTP_SUBNETMASK is not set
# CONFIG_BOOTP_PXE is not set
# CONFIG_CMD_MII is not set
CONFIG_CMD_RTC=y
CONFIG_CMD_TIME=y
CONFIG_CMD_HASH=y
CONFIG_HASH_VERIFY=y
CONFIG_CMD_TPM=y
CONFIG_CMD_EXT4_WRITE=y
CONFIG_CMD_LOG=y
CONFIG_CMD_UBI=y
# CONFIG_ISO_PARTITION is not set
# CONFIG_SPL_EFI_PARTITION is not set
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT=y
CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_USE_ENV_SPI_BUS=y
CONFIG_ENV_SPI_BUS=0
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_NET_RANDOM_ETHADDR=y
# CONFIG_CMD_NFS is not set
CONFIG_TFTP_PORT=y
CONFIG_TFTP_TSIZE=y
CONFIG_BOOTP_SERVERIP=y
CONFIG_BOOTP_MAX_ROOT_PATH_LEN=512
CONFIG_USE_NETMASK=y
CONFIG_NETMASK="255.255.0.0"
CONFIG_USE_SERVERIP=y
CONFIG_SERVERIP="192.168.128.180"
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_BUTTON=y
CONFIG_BUTTON_GPIO=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_CLK_CCF=y
CONFIG_CLK_TI_SCI=y
CONFIG_DFU_MMC=y
CONFIG_DFU_RAM=y
CONFIG_DFU_SF=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_SPL_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_DM_I2C_GPIO=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_MMC_IO_VOLTAGE=y
CONFIG_MMC_UHS_SUPPORT=y
CONFIG_MMC_HS400_SUPPORT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_ADMA=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_DM_MTD=y
CONFIG_DM_SPI_FLASH=y
CONFIG_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPI_FLASH_SOFT_RESET=y
CONFIG_SPI_FLASH_SOFT_RESET_ON_BOOT=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_SPI_FLASH_SPANSION=y
CONFIG_SPI_FLASH_S28HX_T=y
CONFIG_SPI_FLASH_S28HS512T=y
CONFIG_SPI_FLASH_STMICRO=y
CONFIG_SPI_FLASH_MT35XU=y
CONFIG_SPI_FLASH_MTD=y
CONFIG_MULTIPLEXER=y
CONFIG_MUX_MMIO=y
CONFIG_PHY_REALTEK=y
CONFIG_PHY_FIXED=y
CONFIG_TI_AM65_CPSW_NUSS=y
CONFIG_PHY=y
CONFIG_SPL_PHY=y
CONFIG_PHY_CADENCE_SIERRA=y
CONFIG_PHY_J721E_WIZ=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_DM_REGULATOR=y
CONFIG_DM_REGULATOR_FIXED=y
CONFIG_DM_REGULATOR_GPIO=y
CONFIG_RAM=y
CONFIG_SPL_RAM=y
CONFIG_REMOTEPROC_TI_K3_DSP=y
CONFIG_REMOTEPROC_TI_K3_R5F=y
CONFIG_DM_RTC=y
CONFIG_RTC_DS1374=y
CONFIG_SCSI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_QSPI_PHY=y
CONFIG_OMAP3_SPI=y
CONFIG_DM_THERMAL=y
CONFIG_TPM2_TIS_SPI=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_XHCI_HCD=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_USB_CDNS3_HOST=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
CONFIG_USB_GADGET_DOWNLOAD=y
CONFIG_SPL_DFU=y
CONFIG_UFS=y
CONFIG_CADENCE_UFS=y
CONFIG_TI_J721E_UFS=y
CONFIG_WATCHDOG_TIMEOUT_MSECS=150000
CONFIG_WDT=y
CONFIG_WDT_DS1374=y
CONFIG_FS_EXFAT=y
CONFIG_TPM=y
CONFIG_SPL_TPM=y
CONFIG_MOXA_BIOS=y
CONFIG_CMD_MOXA_BIOS=y
CONFIG_MOXA_LIB=y
CONFIG_MOXA_LOG=y
CONFIG_MOXA_LOG_FLASH_OFFSET=0xC60000
CONFIG_MOXA_LOG_FLASH_SIZE=0x100000
CONFIG_MOXA_LOG_FLASH_BUF_ADDR=0x8A000000
CONFIG_MOXA_SYSTEM=y
CONFIG_MOXA_BOOT=y
CONFIG_MOXA_BOOT_MANAGEMENT=y
CONFIG_MOXA_UBOOT_START_OFFSET=0x700000
CONFIG_MOXA_UBOOT2_START_OFFSET=0x950000
CONFIG_MOXA_PASSWORD=y
CONFIG_MOXA_PSWD_START_OFFSET=0xC40000
CONFIG_MOXA_UPGRADE=y
CONFIG_MOXA_SECURE_UPG=y
CONFIG_MOXA_RFI=y
CONFIG_MOXA_MIL_REPLICA=y
#CONFIG_MOXA_TPM_HW_PCR_EXTERN=y
CONFIG_MOXA_ENV_MVAR=y
CONFIG_TI_HAB=y
#CONFIG_MOXA_FLASH_HAB=y
CONFIG_MOXA_BIOS_RELEASE_INFO=y

configs/j7200_evm_r5_defconfig

CONFIG_ARM=y
CONFIG_ARCH_K3=y
CONFIG_SYS_MALLOC_LEN=0x2000000
CONFIG_SYS_MALLOC_F_LEN=0x70000
# CONFIG_TI_I2C_BOARD_DETECT is not set
CONFIG_SPL_GPIO=y
CONFIG_SPL_LIBCOMMON_SUPPORT=y
CONFIG_SPL_LIBGENERIC_SUPPORT=y
CONFIG_NR_DRAM_BANKS=2
CONFIG_SOC_K3_J721E=y
CONFIG_K3_EARLY_CONS=y
CONFIG_TARGET_J7200_R5_EVM=y
CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
CONFIG_SF_DEFAULT_SPEED=40000000
CONFIG_SF_DEFAULT_MODE=0
CONFIG_ENV_SIZE=0x20000
CONFIG_ENV_OFFSET=0xC00000
CONFIG_ENV_SECT_SIZE=0x20000
CONFIG_DM_GPIO=y
CONFIG_SPL_DM_SPI=y
CONFIG_DEFAULT_DEVICE_TREE="k3-j7200-r5-common-proc-board"
# CONFIG_SPL_DFU is not set
CONFIG_SPL_TEXT_BASE=0x41c00000
CONFIG_DM_RESET=y
CONFIG_SPL_MMC=y
CONFIG_SPL_SERIAL=y
CONFIG_SPL_DRIVERS_MISC=y
CONFIG_SPL_STACK_R_ADDR=0x82000000
CONFIG_ENV_OFFSET_REDUND=0xC20000
CONFIG_SPL_FS_FAT=y
CONFIG_SPL_LIBDISK_SUPPORT=y
CONFIG_SPL_SPI_FLASH_SUPPORT=y
CONFIG_SPL_SPI=y
# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
CONFIG_SPL_LOAD_FIT=y
CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
CONFIG_SYS_BOOTM_LEN=0x4000000
CONFIG_USE_BOOTCOMMAND=y
# CONFIG_DISPLAY_CPUINFO is not set
CONFIG_SPL_MAX_SIZE=0xc0000
CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
CONFIG_SPL_BSS_MAX_SIZE=0xa000
CONFIG_SPL_BOARD_INIT=y
CONFIG_SPL_STACK_R=y
CONFIG_SPL_SEPARATE_BSS=y
CONFIG_SPL_SYS_MALLOC=y
CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y
CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x84000000
CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000
CONFIG_SPL_EARLY_BSS=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x800
CONFIG_SPL_DMA=y
CONFIG_SPL_FS_EXT4=y
CONFIG_SPL_I2C=y
CONFIG_SPL_DM_MAILBOX=y
CONFIG_SPL_MTD=y
CONFIG_SPL_DM_SPI_FLASH=y
CONFIG_SPL_NOR_SUPPORT=y
CONFIG_SPL_DM_RESET=y
CONFIG_SPL_POWER_DOMAIN=y
CONFIG_SPL_RAM_SUPPORT=y
CONFIG_SPL_RAM_DEVICE=y
CONFIG_SPL_REMOTEPROC=y
# CONFIG_SPL_SPI_FLASH_TINY is not set
CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
CONFIG_SPL_SPI_LOAD=y
CONFIG_SYS_SPI_U_BOOT_OFFS=0x550000
CONFIG_SPL_THERMAL=y
CONFIG_SPL_YMODEM_SUPPORT=y
CONFIG_HUSH_PARSER=y
CONFIG_CMD_DFU=y
CONFIG_CMD_GPT=y
CONFIG_CMD_MMC=y
CONFIG_CMD_REMOTEPROC=y
# CONFIG_CMD_SETEXPR is not set
# CONFIG_CMD_NET is not set
CONFIG_CMD_TIME=y
CONFIG_CMD_FAT=y
CONFIG_OF_CONTROL=y
CONFIG_SPL_OF_CONTROL=y
CONFIG_ENV_IS_IN_SPI_FLASH=y
CONFIG_ENV_SECT_SIZE_AUTO=y
CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SPL_DM=y
CONFIG_SPL_DM_SEQ_ALIAS=y
CONFIG_REGMAP=y
CONFIG_SPL_REGMAP=y
CONFIG_SYSCON=y
CONFIG_SPL_SYSCON=y
CONFIG_SPL_OF_TRANSLATE=y
CONFIG_CLK=y
CONFIG_SPL_CLK=y
CONFIG_SPL_CLK_CCF=y
CONFIG_SPL_CLK_K3_PLL=y
CONFIG_SPL_CLK_K3=y
CONFIG_SYS_DFU_DATA_BUF_SIZE=0x40000
CONFIG_DMA_CHANNELS=y
CONFIG_TI_K3_NAVSS_UDMA=y
CONFIG_TI_SCI_PROTOCOL=y
CONFIG_DA8XX_GPIO=y
CONFIG_DM_PCA953X=y
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_OMAP24XX=y
CONFIG_DM_MAILBOX=y
CONFIG_K3_SEC_PROXY=y
CONFIG_FS_LOADER=y
CONFIG_SPL_FS_LOADER=y
CONFIG_ESM_K3=y
CONFIG_K3_AVS0=y
CONFIG_ESM_PMIC=y
CONFIG_SUPPORT_EMMC_BOOT=y
CONFIG_SPL_MMC_HS400_SUPPORT=y
CONFIG_MMC_SDHCI=y
CONFIG_SPL_MMC_SDHCI_ADMA=y
CONFIG_MMC_SDHCI_AM654=y
CONFIG_MTD=y
CONFIG_SPI_FLASH=y
CONFIG_SPI_FLASH_MACRONIX=y
CONFIG_PINCTRL=y
# CONFIG_PINCTRL_GENERIC is not set
CONFIG_SPL_PINCTRL=y
# CONFIG_SPL_PINCTRL_GENERIC is not set
CONFIG_PINCTRL_SINGLE=y
CONFIG_POWER_DOMAIN=y
CONFIG_TI_SCI_POWER_DOMAIN=y
CONFIG_TI_POWER_DOMAIN=y
CONFIG_DM_PMIC=y
CONFIG_DM_REGULATOR=y
CONFIG_SPL_DM_REGULATOR=y
CONFIG_K3_SYSTEM_CONTROLLER=y
CONFIG_REMOTEPROC_TI_K3_ARM64=y
CONFIG_RESET_TI_SCI=y
CONFIG_DM_SERIAL=y
CONFIG_SOC_DEVICE=y
CONFIG_SOC_DEVICE_TI_K3=y
CONFIG_SOC_TI=y
CONFIG_SPI=y
CONFIG_DM_SPI=y
CONFIG_CADENCE_QSPI=y
CONFIG_CADENCE_QSPI_PHY=y
CONFIG_SYSRESET=y
CONFIG_SPL_SYSRESET=y
CONFIG_SYSRESET_TI_SCI=y
CONFIG_DM_THERMAL=y
CONFIG_TIMER=y
CONFIG_SPL_TIMER=y
CONFIG_OMAP_TIMER=y
CONFIG_USB=y
CONFIG_DM_USB_GADGET=y
CONFIG_SPL_DM_USB_GADGET=y
CONFIG_USB_CDNS3=y
CONFIG_USB_CDNS3_GADGET=y
CONFIG_SPL_USB_CDNS3_GADGET=y
CONFIG_USB_GADGET=y
CONFIG_SPL_USB_GADGET=y
CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
CONFIG_USB_GADGET_VENDOR_NUM=0x0451
CONFIG_USB_GADGET_PRODUCT_NUM=0x6164
CONFIG_USB_GADGET_DOWNLOAD=y
# CONFIG_SPL_DFU is not set
CONFIG_FS_EXT4=y
CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
CONFIG_LIB_RATIONAL=y
CONFIG_SPL_LIB_RATIONAL=y

0 Rich Chen 11 days ago in reply to Alvin Chen

TI__Expert 4180 points

Tanmay,

Is there any improper setting in defconfig customer provdied?

BR, Rich

0 Tanmay Patil 11 days ago in reply to Rich Chen

TI__Mastermind 39040 points

Hi Rich,

Can you please share "[u-boot-dir]/build/a72/.config" and "[u-boot-dir]/build/r5/.config" after building the u-boot.

Regards,
Tanmay

0 Alvin Chen 10 days ago in reply to Tanmay Patil

Intellectual 510 points

U-Boot SPL 2024.04-g62074eac-dirty (Sep 24 2025 - 09:53:23 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
size=c, ptr=780c, limit=70000: 41c8d400
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=18, ptr=7824, limit=70000: 41c8d40c
k3_avs temperature-sensor@42040000: supply not found for VD2.
k3_avs temperature-sensor@42040000: Could not program AVS voltage for VD2
size=118, ptr=793c, limit=70000: 41c8d424
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
0
- 0 'i2c@42120000'
- found
size=18, ptr=7954, limit=70000: 41c8d53c
size=8, ptr=795c, limit=70000: 41c8d554
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=24, ptr=7980, limit=70000: 41c8d55c
size=40, ptr=79c0, limit=70000: aligned to 41c8d580
size=40, ptr=7a00, limit=70000: aligned to 41c8d5c0
size=b, ptr=7a0b, limit=70000: 41c8d600
size=18, ptr=7a24, limit=70000: 41c8d60c
size=50, ptr=7a74, limit=70000: 41c8d624
size=10, ptr=7a84, limit=70000: 41c8d674
0
- 0 'i2c@42120000'
- found

DDR type: Micron LPDDR4 4G

0
- 0 'i2c@42120000'
- found
0
- 0 'i2c@42120000'
- found
0
- 0 'i2c@42120000'
- found
Trying to boot from SPI
0
- 0 'spi@47040000'
- found
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=50000000 max-frequency=40000000 page-size=256
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
_spi_get_bus_and_cs: bus=41c865b8, slave=840001c8
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for reset-controller
Looking for reset-controller
- checking reset-controller
- result for reset-controller: reset-controller (ret=0)
- result for reset-controller: reset-controller (ret=0)
1
- 0 'sysctrler'
- 1 'a72@0'
- found
Starting ATF on ARM64 core...

1
- 0 'sysctrler'
- 1 'a72@0'
- found
NOTICE: BL31: v2.10.0(release):62074eac-dirty
NOTICE: BL31: Built : 09:53:49, Sep 24 2025
I/TC:
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-g62074eac-dirty (Sep 24 2025 - 09:54:58 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
0
- 0 'i2c@42120000'
- found
size=28, ptr=2ba8, limit=8000: 8047ab80
size=8, ptr=2bb0, limit=8000: 8047aba8
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=38, ptr=2be8, limit=8000: 8047abb0
size=40, ptr=2c40, limit=8000: aligned to 8047ac00
size=40, ptr=2c80, limit=8000: aligned to 8047ac40
size=b, ptr=2c8b, limit=8000: 8047ac80
size=30, ptr=2cc0, limit=8000: 8047ac90
size=98, ptr=2d58, limit=8000: 8047acc0
size=10, ptr=2d68, limit=8000: 8047ad58
0
- 0 'i2c@42120000'
- found
1
- 0 'i2c@42120000'
- 1 'i2c@2000000'
- found
size=28, ptr=28, limit=400000: 81c00000
size=8, ptr=30, limit=400000: 81c00028
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=40, ptr=80, limit=400000: aligned to 81c00040
size=40, ptr=c0, limit=400000: aligned to 81c00080
size=b, ptr=cb, limit=400000: 81c000c0
size=98, ptr=168, limit=400000: 81c000d0
size=10, ptr=178, limit=400000: 81c00168
Trying to boot from SPI
0
- 0 'spi@47040000'
- found
size=8, ptr=180, limit=400000: 81c00178
size=f8, ptr=278, limit=400000: 81c00180
size=c, ptr=284, limit=400000: 81c00278
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=500000000 max-frequency=40000000 page-size=256
size=20, ptr=2a8, limit=400000: 81c00288
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=40, ptr=300, limit=400000: aligned to 81c002c0
size=38, ptr=338, limit=400000: 81c00300
size=40, ptr=380, limit=400000: aligned to 81c00340
size=40, ptr=3c0, limit=400000: aligned to 81c00380
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
size=4, ptr=3c4, limit=400000: 81c003c0
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
size=298, ptr=660, limit=400000: 81c003c8
size=298, ptr=8f8, limit=400000: 81c00660
size=30, ptr=928, limit=400000: 81c008f8
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
size=40, ptr=980, limit=400000: aligned to 81c00940
size=120, ptr=aa0, limit=400000: 81c00980
size=4, ptr=aa4, limit=400000: 81c00aa0
size=68, ptr=b10, limit=400000: 81c00aa8
size=40, ptr=b80, limit=400000: aligned to 81c00b40
size=4, ptr=b84, limit=400000: 81c00b80
size=40, ptr=c00, limit=400000: aligned to 81c00bc0
size=40, ptr=c40, limit=400000: aligned to 81c00c00
size=7440, ptr=8080, limit=400000: aligned to 81c00c40
size=40, ptr=80c0, limit=400000: aligned to 81c08080
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
size=40, ptr=8100, limit=400000: aligned to 81c080c0
size=900, ptr=8a00, limit=400000: aligned to 81c08100
size=40, ptr=8a40, limit=400000: aligned to 81c08a00
size=480, ptr=8ec0, limit=400000: aligned to 81c08a40
size=40, ptr=8f00, limit=400000: aligned to 81c08ec0
size=40, ptr=8f40, limit=400000: aligned to 81c08f00
size=c00, ptr=9b40, limit=400000: aligned to 81c08f40
size=40, ptr=9b80, limit=400000: aligned to 81c09b40
size=8, ptr=9b88, limit=400000: 81c09b80
size=40, ptr=9c00, limit=400000: aligned to 81c09bc0
size=40, ptr=9c40, limit=400000: aligned to 81c09c00
size=40, ptr=9c80, limit=400000: aligned to 81c09c40
size=8, ptr=9c88, limit=400000: 81c09c80
size=40, ptr=9d00, limit=400000: aligned to 81c09cc0
size=40, ptr=9d40, limit=400000: aligned to 81c09d00
size=40, ptr=9d80, limit=400000: aligned to 81c09d40
size=4, ptr=9d84, limit=400000: 81c09d80
size=40, ptr=9e00, limit=400000: aligned to 81c09dc0
size=40, ptr=9e40, limit=400000: aligned to 81c09e00
size=400, ptr=a240, limit=400000: aligned to 81c09e40
size=80, ptr=a2c0, limit=400000: aligned to 81c0a240
size=80, ptr=a340, limit=400000: aligned to 81c0a2c0
size=c0, ptr=a400, limit=400000: aligned to 81c0a340
size=40, ptr=a440, limit=400000: aligned to 81c0a400
size=80, ptr=a4c0, limit=400000: aligned to 81c0a440
size=80, ptr=a540, limit=400000: aligned to 81c0a4c0
size=c0, ptr=a600, limit=400000: aligned to 81c0a540
size=40, ptr=a640, limit=400000: aligned to 81c0a600
size=80, ptr=a6c0, limit=400000: aligned to 81c0a640
size=80, ptr=a740, limit=400000: aligned to 81c0a6c0
size=c0, ptr=a800, limit=400000: aligned to 81c0a740
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
_spi_get_bus_and_cs: bus=804790e0, slave=81c008f8
size=80, ptr=a880, limit=400000: aligned to 81c0a800
size=80, ptr=a900, limit=400000: aligned to 81c0a880
size=100, ptr=aa00, limit=400000: aligned to 81c0a900
size=80, ptr=aa80, limit=400000: aligned to 81c0aa00
size=80, ptr=ab00, limit=400000: aligned to 81c0aa80
size=100, ptr=ac00, limit=400000: aligned to 81c0ab00
SPL: replica=0
SPL: Normal mode..
size=80, ptr=ac80, limit=400000: aligned to 81c0ac00
size=80, ptr=ad00, limit=400000: aligned to 81c0ac80
size=c0, ptr=adc0, limit=400000: aligned to 81c0ad00
size=163f80, ptr=16ed40, limit=400000: aligned to 81c0adc0
size=80, ptr=16edc0, limit=400000: aligned to 81d6ed40
size=80, ptr=16ee40, limit=400000: aligned to 81d6edc0
size=100, ptr=16ef40, limit=400000: aligned to 81d6ee40
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted

U-Boot 2024.04-g62074eac-dirty (Sep 24 2025 - 09:54:58 +0800)

SoC: J7200 SR2.0 GP
Model: Texas Instruments J7200 EVM
DRAM: 4 GiB
Core: 105 devices, 32 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
WDT: Started with servicing (15s timeout)
MMC: mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from SPIFlash... cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=0000000047040000 ahbbase=0000000500000000 max-frequency=40000000 page-size=256
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
*** Warning - bad CRC, using default environment

In: serial@2800000
Out: serial@2800000
Err: serial@2800000
Net: Address in environment is 00:90:e8:33:81:01
eth0: ethernet@46000000port@1, eth1: ethernet@c000000port@1, eth2: ethernet@c000000port@2, eth3: ethernet@c000000port@3
tpm@0 v2.0: VendorID 0x15d1, DeviceID 0x001d, RevisionID 0x36 [open]
jedec_spi_nor flash@0: Software reset enable failed: -524
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
jedec_spi_nor flash@0: Software reset enable failed: -524
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
device 0 offset 0xc60000, size 0x100000
SF: 1048576 bytes @ 0xc60000 Read: OK
LOG: Storage as empty, create a new one.
jedec_spi_nor flash@0: Software reset enable failed: -524
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
device 0 offset 0xc60000, size 0x100000
1048576 bytes written, 0 bytes skipped in 9.180s, speed 116914 B/s
Saving Environment to SPIFlash... Erasing SPI flash...Writing to SPI flash...done
Valid environment: 2
OK
Press <DEL> To Enter BIOS configuration Setting 0 1

0 Tanmay Patil 10 days ago in reply to Alvin Chen

TI__Mastermind 39040 points

Hi,

It seems that the clock is being set to 33.33 MHz. This must be because of the the clock divisor we have in OSPI controller are only even numbers. To the best it can do below 40MHz is 33.333 MHz (200/6).

This should be consistent with your oscilloscope readings.

When the parent clock is 166.66MHz, the best possible clock is with DIV value 6 which tuns out to be 27.77 MHz.

Regards,
Tanmay

0 Bo Mellberg 10 days ago in reply to Tanmay Patil

Intellectual 581 points

I have managed to get 40 MHz by defining a parent clock for ospi1 and setting it to 80 MHz. Pretty much what is already done for ospi0.

&ospi1 {
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&mcu_fss0_ospi1_pins_default>;

	assigned-clocks = <&k3_clks 104 0>;			/* DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK */
	assigned-clock-parents = <&k3_clks 104 1>;	/* DEV_MCU_FSS0_OSPI_1_OSPI_RCLK_CLK_PARENT_HSDIV4_16FFT_MCU_1_HSDIVOUT4_CLK */
	assigned-clock-rates = <80000000>;

	flash@0 {
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-tx-bus-width = <1>;
		spi-rx-bus-width = <4>;
		spi-max-frequency = <40000000>;
		cdns,tshsl-ns = <60>;
		cdns,tsd2d-ns = <60>;
		cdns,tchsh-ns = <60>;
		cdns,tslch-ns = <60>;
		cdns,read-delay = <2>;

Tanmay Patil Do you see anything wrong with this setup?

A boot log shows actual clock is now 40 MHz, and the oscilloscope verifies it correctly.

U-Boot SPL 2024.04-ti-gda00c65d74dc (Sep 24 2025 - 09:32:35 +0000)
SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.8--v11.01.08 (Fancy Rat)')
Trying to boot from SPI
cadence_spi spi@47050000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47050000 ahbbase=58000000 max-frequency=40000000 page-size=256
cadence_qspi_apb_config_baudrate_div: ref_clk 80000000Hz sclk 40000000Hz Div 0x0, actual 40000000Hz
cadence_spi_set_speed: speed=40000000
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_config_baudrate_div: ref_clk 80000000Hz sclk 40000000Hz Div 0x0, actual 40000000Hz
cadence_spi_set_speed: speed=40000000
cadence_qspi_apb_chipselect : chipselect 0 decode 0
cadence_qspi_apb_chipselect : chipselect 0 decode 0
Authentication passed
Authentication passed
Authentication passed
Loading Environment from nowhere... OK
Authentication passed
Authentication passed
Starting ATF on ARM64 core...

Regards,

/Bo

0 Rich Chen 9 days ago in reply to Bo Mellberg

TI__Expert 4180 points

Tanmay,

My customer is also able to modify clock now after changing clock source to 200Mhz PLL.

The clock measurement is as expected and it can see 100Mhz clock but the error rate will go up significantly.

However, the reason why the access time is still slow is because DRA821 OSPI0 is using dual read mode to access QSPI flash.

There are only two data pins are used and there is no way to run with 4 data pins (quad read).

I found your setting to spi bus width is as below

spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>;

Customer can only set

spi-tx-bus-width = <8>;
spi-rx-bus-width = <8>;

but OSPI controller will run in dual read mode only.

Force to set as same as you will not work.

We suspect this could be related to QE bit setting inside flash model customer use. The QSPI lash model is Marconix MX25L25645G.

We force to set QE bit to 1 by using programming tool.

Not sure why OSPI controller cannot switch to Quad Read mode.

Any suggestion or check point?

BR, Rich

0 Alvin Chen 9 days ago in reply to Rich Chen

Intellectual 510 points

U-Boot SPL 2024.04-g62074eac-dirty (Sep 24 2025 - 18:11:11 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
size=c, ptr=780c, limit=70000: 41c8d400
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=18, ptr=7824, limit=70000: 41c8d40c
k3_avs temperature-sensor@42040000: supply not found for VD2.
k3_avs temperature-sensor@42040000: Could not program AVS voltage for VD2
size=118, ptr=793c, limit=70000: 41c8d424
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
0
- 0 'i2c@42120000'
- found
size=18, ptr=7954, limit=70000: 41c8d53c
size=8, ptr=795c, limit=70000: 41c8d554
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=24, ptr=7980, limit=70000: 41c8d55c
size=40, ptr=79c0, limit=70000: aligned to 41c8d580
size=40, ptr=7a00, limit=70000: aligned to 41c8d5c0
size=b, ptr=7a0b, limit=70000: 41c8d600
size=18, ptr=7a24, limit=70000: 41c8d60c
size=50, ptr=7a74, limit=70000: 41c8d624
size=10, ptr=7a84, limit=70000: 41c8d674
0
- 0 'i2c@42120000'
- found

DDR type: Micron LPDDR4 4G

0
- 0 'i2c@42120000'
- found
0
- 0 'i2c@42120000'
- found
0
- 0 'i2c@42120000'
- found
Trying to boot from SPI
0
- 0 'spi@47040000'
- found
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=50000000 max-frequency=40000000 page-size=256
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
_spi_get_bus_and_cs: bus=41c865b8, slave=840001c8
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for reset-controller
Looking for reset-controller
- checking reset-controller
- result for reset-controller: reset-controller (ret=0)
- result for reset-controller: reset-controller (ret=0)
1
- 0 'sysctrler'
- 1 'a72@0'
- found
Starting ATF on ARM64 core...

1
- 0 'sysctrler'
- 1 'a72@0'
- found
NOTICE: BL31: v2.10.0(release):62074eac-dirty
NOTICE: BL31: Built : 18:11:41, Sep 24 2025
I/TC:
I/TC: Primary CPU initializing
I/TC: SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
I/TC: HUK Initialized
I/TC: Activated SA2UL device
I/TC: Fixing SA2UL firewall owner for GP device
I/TC: Enabled firewalls for SA2UL TRNG device
I/TC: SA2UL TRNG initialized
I/TC: SA2UL Drivers initialized
I/TC: Primary CPU switching to normal world boot

U-Boot SPL 2024.04-g62074eac-dirty (Sep 24 2025 - 18:13:00 +0800)
SYSFW ABI: 4.0 (firmware rev 0x000a '10.0.8--v10.00.08 (Fiery Fox)')
0
- 0 'i2c@42120000'
- found
size=28, ptr=2ba8, limit=8000: 8047ab80
size=8, ptr=2bb0, limit=8000: 8047aba8
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=38, ptr=2be8, limit=8000: 8047abb0
size=40, ptr=2c40, limit=8000: aligned to 8047ac00
size=40, ptr=2c80, limit=8000: aligned to 8047ac40
size=b, ptr=2c8b, limit=8000: 8047ac80
size=30, ptr=2cc0, limit=8000: 8047ac90
size=98, ptr=2d58, limit=8000: 8047acc0
size=10, ptr=2d68, limit=8000: 8047ad58
0
- 0 'i2c@42120000'
- found
1
- 0 'i2c@42120000'
- 1 'i2c@2000000'
- found
size=28, ptr=28, limit=400000: 81c00000
size=8, ptr=30, limit=400000: 81c00028
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=40, ptr=80, limit=400000: aligned to 81c00040
size=40, ptr=c0, limit=400000: aligned to 81c00080
size=b, ptr=cb, limit=400000: 81c000c0
size=98, ptr=168, limit=400000: 81c000d0
size=10, ptr=178, limit=400000: 81c00168
Trying to boot from SPI
0
- 0 'spi@47040000'
- found
size=8, ptr=180, limit=400000: 81c00178
size=f8, ptr=278, limit=400000: 81c00180
size=c, ptr=284, limit=400000: 81c00278
cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=47040000 ahbbase=500000000 max-frequency=40000000 page-size=256
size=20, ptr=2a8, limit=400000: 81c00288
Looking for power-controller
Looking for power-controller
- checking power-controller
- result for power-controller: power-controller (ret=0)
- result for power-controller: power-controller (ret=0)
size=40, ptr=300, limit=400000: aligned to 81c002c0
size=38, ptr=338, limit=400000: 81c00300
size=40, ptr=380, limit=400000: aligned to 81c00340
size=40, ptr=3c0, limit=400000: aligned to 81c00380
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
size=4, ptr=3c4, limit=400000: 81c003c0
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
Looking for clock-controller
Looking for clock-controller
- checking clock-controller
- result for clock-controller: clock-controller (ret=0)
- result for clock-controller: clock-controller (ret=0)
size=298, ptr=660, limit=400000: 81c003c8
size=298, ptr=8f8, limit=400000: 81c00660
size=30, ptr=928, limit=400000: 81c008f8
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
size=40, ptr=980, limit=400000: aligned to 81c00940
size=120, ptr=aa0, limit=400000: 81c00980
size=4, ptr=aa4, limit=400000: 81c00aa0
size=68, ptr=b10, limit=400000: 81c00aa8
size=40, ptr=b80, limit=400000: aligned to 81c00b40
size=4, ptr=b84, limit=400000: 81c00b80
size=40, ptr=c00, limit=400000: aligned to 81c00bc0
size=40, ptr=c40, limit=400000: aligned to 81c00c00
size=7440, ptr=8080, limit=400000: aligned to 81c00c40
size=40, ptr=80c0, limit=400000: aligned to 81c08080
k3-navss-ringacc ringacc@2b800000: Ring Accelerator probed rings:286, gp-rings[96,32] sci-dev-id:235
k3-navss-ringacc ringacc@2b800000: dma-ring-reset-quirk: disabled
size=40, ptr=8100, limit=400000: aligned to 81c080c0
size=900, ptr=8a00, limit=400000: aligned to 81c08100
size=40, ptr=8a40, limit=400000: aligned to 81c08a00
size=480, ptr=8ec0, limit=400000: aligned to 81c08a40
size=40, ptr=8f00, limit=400000: aligned to 81c08ec0
size=40, ptr=8f40, limit=400000: aligned to 81c08f00
size=c00, ptr=9b40, limit=400000: aligned to 81c08f40
size=40, ptr=9b80, limit=400000: aligned to 81c09b40
size=8, ptr=9b88, limit=400000: 81c09b80
size=40, ptr=9c00, limit=400000: aligned to 81c09bc0
size=40, ptr=9c40, limit=400000: aligned to 81c09c00
size=40, ptr=9c80, limit=400000: aligned to 81c09c40
size=8, ptr=9c88, limit=400000: 81c09c80
size=40, ptr=9d00, limit=400000: aligned to 81c09cc0
size=40, ptr=9d40, limit=400000: aligned to 81c09d00
size=40, ptr=9d80, limit=400000: aligned to 81c09d40
size=4, ptr=9d84, limit=400000: 81c09d80
size=40, ptr=9e00, limit=400000: aligned to 81c09dc0
size=40, ptr=9e40, limit=400000: aligned to 81c09e00
size=400, ptr=a240, limit=400000: aligned to 81c09e40
size=80, ptr=a2c0, limit=400000: aligned to 81c0a240
size=80, ptr=a340, limit=400000: aligned to 81c0a2c0
size=c0, ptr=a400, limit=400000: aligned to 81c0a340
size=40, ptr=a440, limit=400000: aligned to 81c0a400
size=80, ptr=a4c0, limit=400000: aligned to 81c0a440
size=80, ptr=a540, limit=400000: aligned to 81c0a4c0
size=c0, ptr=a600, limit=400000: aligned to 81c0a540
size=40, ptr=a640, limit=400000: aligned to 81c0a600
size=80, ptr=a6c0, limit=400000: aligned to 81c0a640
size=80, ptr=a740, limit=400000: aligned to 81c0a6c0
size=c0, ptr=a800, limit=400000: aligned to 81c0a740
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
_spi_get_bus_and_cs: bus=804790e0, slave=81c008f8
size=80, ptr=a880, limit=400000: aligned to 81c0a800
size=80, ptr=a900, limit=400000: aligned to 81c0a880
size=100, ptr=aa00, limit=400000: aligned to 81c0a900
size=80, ptr=aa80, limit=400000: aligned to 81c0aa00
size=80, ptr=ab00, limit=400000: aligned to 81c0aa80
size=100, ptr=ac00, limit=400000: aligned to 81c0ab00
SPL: replica=0
SPL: Normal mode..
size=80, ptr=ac80, limit=400000: aligned to 81c0ac00
size=80, ptr=ad00, limit=400000: aligned to 81c0ac80
size=c0, ptr=adc0, limit=400000: aligned to 81c0ad00
size=163fc0, ptr=16ed80, limit=400000: aligned to 81c0adc0
size=80, ptr=16ee00, limit=400000: aligned to 81d6ed80
size=80, ptr=16ee80, limit=400000: aligned to 81d6ee00
size=100, ptr=16ef80, limit=400000: aligned to 81d6ee80
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted
Warning: Detected image signing certificate on GP device. Skipping certificate to prevent boot failure. This will fail if the image was also encrypted

U-Boot 2024.04-g62074eac-dirty (Sep 24 2025 - 18:13:00 +0800)

SoC: J7200 SR2.0 GP
Model: Texas Instruments J7200 EVM
DRAM: 4 GiB
mode : 49152 ----------
mode : 0 ----------
Core: 105 devices, 32 uclasses, devicetree: separate
Warning: Device tree includes old 'u-boot,dm-' tags: please fix by 2023.07!
WDT: Started with servicing (15s timeout)
MMC: mmc@4f80000: 0, mmc@4fb0000: 1
Loading Environment from SPIFlash... cadence_spi spi@47040000: Unable to find PHY pattern partition
cadence_spi_of_to_plat: regbase=0000000047040000 ahbbase=0000000500000000 max-frequency=40000000 page-size=256
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
OK
In: serial@2800000
Out: serial@2800000
Err: serial@2800000
Net: Address in environment is 00:90:e8:33:81:01
eth0: ethernet@46000000port@1, eth1: ethernet@c000000port@1, eth2: ethernet@c000000port@2, eth3: ethernet@c000000port@3
Date: 2000-01-01 (Saturday) Time: 0:00:25
RTC: OK
tpm@0 v2.0: VendorID 0x15d1, DeviceID 0x001d, RevisionID 0x36 [open]
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
SF: Detected mx25l25635e with page size 256 Bytes, erase size 4 KiB, total 32 MiB
--------------- div = 2 , (2 * (div + 1) = 6 -----------------
cadence_qspi_apb_config_baudrate_div: ref_clk 200000000Hz sclk 40000000Hz Div 0x2, actual 33333333Hz
cadence_spi_write_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
cadence_spi_set_speed: speed=40000000
device 0 offset 0xc60000, size 0x100000
SF: 1048576 bytes @ 0xc60000 Read: OK
Press <DEL> To Enter BIOS configuration Setting: 0

0 Rich Chen 8 days ago in reply to Alvin Chen

TI__Expert 4180 points

Tanmay,

Customer compare build/a72/.config with build/A53/.config they used in AM62x and AM64x and not find any missing change or setting which could be related.

The process for quad mode enable is also executed based on the debug log added in driver.

Customer also verified this Macronix flash on AM62x platform and work on dual mode.

Now we are suspecting flash may not change to Quad Enable mode because software reset is not complete and always get time out.

"jedec_spi_nor flash@0: Software reset enable failed: -524"

I remember you said this is irrelevant when online debug which your log on EVM also show this error log.

Is there any reason why this log is presented but not affect flash behavior?

Could you trace this function and see whether is reasonable?

BR, Rich

0 Rich Chen 2 days ago in reply to Rich Chen

TI__Expert 4180 points

Tanmay,

By changing clock source from clock source 103 (166Mhz) to clock source 104 (200Mhz)

- clocks = <&k3_clks 103 0>;
- assigned-clocks = <&k3_clks 103 0>;
- assigned-clock-parents = <&k3_clks 103 2>;
- assigned-clock-rates = <166666666>;
- power-domains = <&k3_pds 103 TI_SCI_PD_EXCLUSIVE>;
+ cdns,phase-detect-selector = <2>;
+ clocks = <&k3_clks 104 0>;
+ power-domains = <&k3_pds 104 TI_SCI_PD_EXCLUSIVE>;

we can now achieve 50Mhz (/4) and 33.33Mhz (/6) and 25Mhz (/8).

So setting target clock to 40Mhz will get only 33.33Mhz and setting target clock to 50Mhz will get 50Mhz.

The original clock source 103 for OSPI0 is 166Mhz, so customer got 20.75Mhz (/8) when setting target clock at 25Mhz and need to set up to 41.5Mhz to get 41.5Mhz clock.

Back to Macronix flash case, customer capture all the commend waveforms and data by Logic Analyzer to analysis and found customer found it can work at u-boot first boot but it will crash after sf probe.

Looking into the commend issue from DRA821, it will issue reset enable command 66h then stop without getting following command 99h.

two approaches was taken

1. add SPI_NOR_SKIP_SFDP, this one should fix the problem when it crash after sf probe since this QSPI flash support SFDP.

2. Remove softreset

Customer made Macronix flash work with DRA821 normally after removing "softreset" and pass pressure test.

It seems softreset is the root cause for Marconix.

Do you see any risk on removing softreset?

BR, Rich

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DRA821U: QSPI flash operating clock on DRA821U