AM6442: GPIO debounce setting

Takeshi Yamamoto

Part Number: AM6442

Tool/software:

I am trying to set the debounce function for the AM6442 GPIO.

The target GPIOs are GPIO1_64 and GPIO1_65, and I tried to set the period to the "value closest to 1us".
I created the following initialization function and placed it immediately after Board_init() of the application running on the R5F0-1 core.

void DebounceInitialize(void){

    CSL_mcu_ctrl_mmr_cfg0Regs *regs = (CSL_mcu_ctrl_mmr_cfg0Regs *)(uintptr_t)CSL_CTRL_MMR0_CFG0_BASE;

    volatile uint32_t *debounce1Reg = NULL;

    debounce1Reg = &regs->DBOUNCE_CFG1;

    CSL_REG32_WR(debounce1Reg, 53);


    uint32_t            baseAddr;
    volatile uint32_t  *regAddr;
    uint32_t setting;

    baseAddr = CSL_PADCFG_CTRL0_CFG0_BASE + PADCFG_PMUX_OFFSET;

    Pinmux_unlockMMR(PINMUX_DOMAIN_ID_MAIN);

    regAddr = (volatile uint32_t *)(baseAddr + PIN_I2C0_SCL);
    setting = (CSL_REG32_RD(regAddr) | PIN_DEBOUNCE1_ENABLE);
    CSL_REG32_WR(regAddr, setting);


    regAddr = (volatile uint32_t *)(baseAddr + PIN_I2C0_SDA);
    setting = (CSL_REG32_RD(regAddr) | PIN_DEBOUNCE1_ENABLE);
    CSL_REG32_WR(regAddr, setting);

    Pinmux_lockMMR(PINMUX_DOMAIN_ID_MAIN);

    return;
}

To verify that the settings were reflected, I performed the following tests.

- Set an interrupt to "display in debug output" on GPIO1_65.
- Run the application on the AM6442 and input a negative pulse with a width of 0.5us to GPIO1_65.

I predicted that "no interrupt would occur," but in fact an interrupt did occur.

I think there is an error in the initialization procedure and the settings are not as intended.

Please tell me the correct way to set it up.

7 months ago

0 Paula Carrillo 7 months ago

TI__Mastermind 40580 points

Hi I am sending it to our expert, please allow him some time to come back to you

In the meantime, are you using MCU_SDK or Motor Control SDK?

thank you,

Paula

0 Takeshi Yamamoto 7 months ago in reply to Paula Carrillo

Prodigy 55 points

I am using MCU+ SDK version 11.00.00.15.

0 Tushar Thakur 7 months ago in reply to Takeshi Yamamoto

TI__Guru 57288 points

Hi Takeshi,

The GPIO1_64 and GPIO1_65 pin does not support the debounce functionality.

Please refer below image.

Regards,

Tushar

0 Takeshi Yamamoto 6 months ago in reply to Tushar Thakur

Prodigy 55 points

I checked "Table 5-35. GPIO0 Signal Descriptions" in the AM64x datasheet and understood the reason for the setting failure.

Let me just confirm one thing.

Can I assume that the procedure used this time simply targeted the wrong GPIO, and that there was no problem with the setting procedure for the debounce function?

0 Tushar Thakur 6 months ago in reply to Takeshi Yamamoto

TI__Guru 57288 points

Hi Takeshi,

The code you provided above uses the macro CSL_CTRL_MMR0_CFG0_BASE which is for Main domain MMR, but you need to use the CSL_MCU_CTRL_MMR0_CFG0_BASE macro.

You are trying to directly write to the debounce register without performing any unlock/lock operation. Ideally you should unlock the ctrl_mmr first, then write the value and lock it again.

Regards,

Tushar

0 Takeshi Yamamoto 6 months ago in reply to Tushar Thakur

Prodigy 55 points

I have reflected the two comments in the code.

Is this code OK for setting the debounce function for GPIO0_43?

void DebounceInitialize(void){


	CSL_mcu_ctrl_mmr_cfg0Regs *regs = (CSL_mcu_ctrl_mmr_cfg0Regs *)(uintptr_t)CSL_MCU_CTRL_MMR0_CFG0_BASE;

    volatile uint32_t *debounce1Reg = NULL;

	SOC_controlModuleLockMMR(SOC_DOMAIN_ID_MCU, 1);

	debounce1Reg = &regs->DBOUNCE_CFG1;

	SOC_controlModuleUnlockMMR(SOC_DOMAIN_ID_MCU, 1);

	CSL_REG32_WR(debounce1Reg, 53);


    uint32_t            baseAddr;
    volatile uint32_t  *regAddr;
    uint32_t setting;

    baseAddr = CSL_PADCFG_CTRL0_CFG0_BASE + PADCFG_PMUX_OFFSET;

    Pinmux_unlockMMR(PINMUX_DOMAIN_ID_MAIN);

	regAddr = (volatile uint32_t *)(baseAddr + PIN_GPMC0_CSN2);
    setting = (CSL_REG32_RD(regAddr) | PIN_DEBOUNCE1_ENABLE);
    CSL_REG32_WR(regAddr, setting);

    Pinmux_lockMMR(PINMUX_DOMAIN_ID_MAIN);

    return;
}

0 Tushar Thakur 6 months ago in reply to Takeshi Yamamoto

TI__Guru 57288 points

Hi,

The above looks okay. Please check the value of debounce1Reg variable to confirm it is writing to correct address.

Also check the value at address whether it is written correctly or not.

What is the value of PIN_DEBOUNCE1_ENABLE macro here?

Regards,

Tushar

0 Takeshi Yamamoto 6 months ago in reply to Tushar Thakur

Prodigy 55 points

I checked the value of debounce1Reg.

debounce1Reg = 0x4504084

The definition of PIN_DEBOUNCE1_ENABLE is as follows:

#define PIN_DEBOUNCE1_ENABLE (((uint32_t) 0x1U) << 11U)

+1 Tushar Thakur 6 months ago in reply to Takeshi Yamamoto

TI__Guru 57288 points

Hi,

Yes, the above sequence seems okay.

Regards,

Tushar

0 Takeshi Yamamoto 6 months ago in reply to Tushar Thakur

Prodigy 55 points

I was able to confirm that the debounce setting was reflected.

I input 0.5us and 1us pulses to the GPIO and confirmed that the 0.5us pulse was filtered.

Thank you.

Processors

Processors forum

AM6442: GPIO debounce setting