I2C Interface on OMAPL138

Boris,

I2C won't be able to support a free running clock. Have your considered other peripherals such as PWM?

Hello Paul.

Thank you for your respond.

I am trying to use I2C1 SCL for the system self test and need to generate low frequency clock of ~4KHz.

I don't really need "the free running" clock as "all the time running clock".

I need to be able to run the clock from some point ("Start Condition") until I decided to stop the clock ("stop condition").

I have only one master (OMAP-L138) and only one slave.

I looked through the I2C documentation in User Guide (SPRUH77).

If I set ICMDR Register as following:

1.  MST =1 for I2C master

2.  TRX = 1 for Transmitter mode

3.  RM = 1 for continuous I2C transmission

4.  FDF = 1 for "free data format"

5.  BC = "0h" for 8-bit data word.

I will set all the divider registers as required with "reset bit" IRS=0.

After that I will set IRS = 1 and generate "start condition" by setting STT = 1.

I expect the SCL to start after I set STT=1 and run continuously until "stop condition" is generated by setting STP=1 or "reset conditon" by setting IRS=0.

Will SCL look as continuous CLOCK in this time interval - from STT=1 to IRS=0?

Did I understand the I2C interface correctly or I am missing something?

Thank you for your help,

Boris Ruvinsky

802-877-4978

508-740-5002

Hello Paul.

Reading OMAP-L138 I2C documentation - I found DLB bit in ICMDR register.

If I set:

1. DLB=1 for Digital Loopback

2. FDF=0 - FDF=1 is not supported in DLB mode.

3. MST=1

4. TRX=1

5. BC=0

6. RM = 0

6. ICDC="0" for 65536 data words

According to Figure 23-23 on page982 (SPRUH77) - the SCL (of 4KHz for example) can last for ~65536*8/4000 = ~130Sec. That in case if EDMA provides the sufficient data for TX.

Is this correct?

As I understood - the external ACK is not required in DLB mode. Is it correct?

Thank you for your help,

Boris Ruvinsky

The best way would be to just set up the peripheral as a master transmitter and max out the ICCNT register. There will be 9 clocks per byte transmitted (the extra coming from the ACK cycle). You should also set the IGNACK bit of the ICEMDR register if the slave doesn't plan on sending ACKs back.

Jeff

Hello Jeff.

Thank you very much for your respond and information.

I have just one question:

1.  If I2C Pin Function Register set to GPIO mode - the outputs are still Open Drain as in I2C mode?

Thank you,

Boris Ruvinsky

The chip does not use open drain buffers, even in I2C mode. It uses the same buffers as the other IOs except instead of driving high, it automatically configures the IO as an input.

You can mimic the open drain functionality yourself if you are going to bit-bang the interface. In other words, set the GPIO output to 0, and to drive low set it as an output, and for a 1 set it as an input letting the external resistors pull it up.

Jeff

Hello Jeff.

Thank you for your help.

For some reason I can't get the I2C1_SCL running.

I use the following settings:

1. ICCNT = 0 for 65536 data count

2. ICMDR[10]=1 for the "Master"

3. ICMDR[9] = 1 for Transmit

4. ICEMDR[1] = 1 for "Ignore NACK"

5. ICPSC = 0x9 for I2C clock frequency = 80/10=8MHz (SYSCLK4=80MHz) 

6. I2C is enabled through the PSC1_11. PSC1_11 status register retunes 0x1E03 which means I2C1 is ON.

7. PINMUX4 = 0x22442244 - UART_TX/RX, I2C1_SDA/SCL, I2C0_SCL/SDA, GP1[6:7].

I2C0 works OK.

But I2C1 does not generate the SCL - looks dead.

Can you give me an idea what is going wrong?

Thank you for your help,

Boris Ruvinsky

Response moved to new thread

I just noticed that Boris started a new thread asking the same question that I responded to above. It would be better to use that thread instead.