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AM67A: Enable i2c4 on AM67

Part Number: AM67A
Other Parts Discussed in Thread: AM67

Tool/software:

I'm using the device tree settings in the previous post but i2c4 still isn't enabling for me.
I noticed the other i2c devices on AM67 are using "ti,am64-i2c", "ti,omap4-i2c", not the one suggested?
I checked the latest dts but still don't see main_i2c4 enabled on the evm:
git.ti.com/.../k3-j722s-evm.dts

Here's my error:
omap_i2c: probe of bus@f0000:i2c@fe80000 failed with error -22

main_i2c4_pins_default: main_i2c4-default-pins {
pinctrl-single,pins = <
J722S_IOPAD(0x00a8, PIN_INPUT_PULLUP, 1) /* (R27) GPMC0_CSn0.I2C4_SCL */
J722S_IOPAD(0x00ac, PIN_INPUT_PULLUP, 1) /* (P21) GPMC0_CSn1.I2C4_SDA */
>;
};


&cbass_main {
main_i2c4: i2c@fe80000 {
compatible = "ti,j721e-i2c", "ti,omap4-i2c";
reg = <0x00 0x0fe80000 0x00 0x100>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&k3_clks 257 2>;
clock-names = "fck";
power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
};
};

&main_i2c4 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&main_i2c4_pins_default>;
clock-frequency = <100000>;
};

  • Hi Evan,

    You're correct, it should probably be "ti,am64-i2c", "ti,omap4-i2c".

    If you use that instead, do you still see the probe failure error?

    Best,
    Jared

  • Hi Jared,

    With that change, I see:
    omap_i2c bus@f0000:i2c@fe80000: invalid resource (null)
    omap_i2c: probe of bus@f0000:i2c@fe80000 failed with error -22

  • Hi Evan,

    Looking closer, I also realized there is no GIC interrupt for the I2C4.

    Can you try the following:

    	main_i2c4: i2c@fe80000 {
    		compatible = "ti,am64-i2c", "ti,omap4-i2c";
    		reg = <0x00 0xfe80000 0x00 0x100>;
    		interrupts = <&main_gpio_intr 178 IRQ_TYPE_LEVEL_HIGH>;
    		#address-cells = <1>;
    		#size-cells = <0>;
    		power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
    		clocks = <&k3_clks 257 2>;
    		clock-names = "fck";
    		status = "disabled";
    	};

    Best,
    Jared

  • Hi Jared,

    I used "okay" instead of "disabled" getting a new error:
    omap_i2c bus@f0000:i2c@fe80000: error -6: IRQ index 0 not found

  • Hi Evan,

    Can you try:

    	main_i2c4: i2c@fe80000 {
    		compatible = "ti,am64-i2c", "ti,omap4-i2c";
    		reg = <0x00 0xfe80000 0x00 0x100>;
    		interrupt-parent = <&main_gpio_intr>;
    		interrupts = <178>;
    		#address-cells = <1>;
    		#size-cells = <0>;
    		power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
    		clocks = <&k3_clks 257 2>;
    		clock-names = "fck";
    		status = "disabled";
    	};

    Best,
    Jared

  • Hi Jared,

    status='disabled' will not initialize the peripheral. I'm getting the same behavior when using 'okay'
    On our boards main_i2c4 will map to i2c-5.

    kernel[640]: omap_i2c bus@f0000:i2c@fe80000: invalid resource (null)
    kernel[640]: omap_i2c: probe of bus@f0000:i2c@fe80000 failed with error -22

    Thanks

  • Hi Jared,

    I found that 257 for clock and power domain is the first issue.
    I set it to 0x6c and now it's deferring the probe indefinitely.

  • Hi Jared,

    I also tried 0x65 and see it defer probe forever.

    Where does the 257 value come from?

  • Hi Jared,

    Looks like maybe it's printing invalid resource when it calls into:

    omap->base = devm_platform_ioremap_resource(pdev, 0);

    Is there another location that I need to set up the fe80000 address to map to i2c?

    For example, I don't have it mapped in u-boot, only the dtb for the kernel on the A53 cores.
  • Hi Evan,

    The issue is likely because the memory is not mapped in the cbass_main reg property.

    j722s-main.dtsi:

    cbass_main: bus@f0000 {
    		compatible = "simple-bus";
    		#address-cells = <2>;
    		#size-cells = <2>;
    
    		ranges = <0x00 0x000f0000 0x00 0x000f0000 0x00 0x00030000>, /* Main MMRs */
    			 <0x00 0x00420000 0x00 0x00420000 0x00 0x00001000>, /* ESM0 */
    			 <0x00 0x00600000 0x00 0x00600000 0x00 0x00001100>, /* GPIO */
    			 <0x00 0x00703000 0x00 0x00703000 0x00 0x00000200>, /* USB0 debug trace */
    			 <0x00 0x0070c000 0x00 0x0070c000 0x00 0x00000200>, /* USB1 debug trace */
    			 <0x00 0x00a40000 0x00 0x00a40000 0x00 0x00000800>, /* Timesync router */
    			 <0x00 0x01000000 0x00 0x01000000 0x00 0x01b28400>, /* First peripheral window */
    			 <0x00 0x08000000 0x00 0x08000000 0x00 0x00200000>, /* Main CPSW */
    			 <0x00 0x0d000000 0x00 0x0d000000 0x00 0x00800000>, /* PCIE_0 */
    			 <0x00 0x0e000000 0x00 0x0e000000 0x00 0x01d20000>, /* Second peripheral window */
    			 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
    			 <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
    			 <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
    			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
    			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
    			 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
    			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
    			 <0x00 0x30200000 0x00 0x30200000 0x00 0x00010000>, /* DSS */
    			 <0x00 0x30210000 0x00 0x30210000 0x00 0x00010000>, /* VPU */
    			 <0x00 0x30220000 0x00 0x30220000 0x00 0x00010000>, /* DSS1 */
    			 <0x00 0x30270000 0x00 0x30270000 0x00 0x00010000>, /* DSI-base1 */
    			 <0x00 0x30300000 0x00 0x30300000 0x00 0x00001000>, /* MCRC64 */
    			 <0x00 0x30500000 0x00 0x30500000 0x00 0x00100000>, /* DSI-base2 */
    			 <0x00 0x31000000 0x00 0x31000000 0x00 0x00050000>, /* USB0 DWC3 Core window */
    			 <0x00 0x31200000 0x00 0x31200000 0x00 0x00040000>, /* USB1 DWC3 Core window */
    			 <0x00 0x40900000 0x00 0x40900000 0x00 0x00030000>, /* SA3UL */
    			 <0x00 0x43600000 0x00 0x43600000 0x00 0x00010000>, /* SA3 sproxy data */
    			 <0x00 0x44043000 0x00 0x44043000 0x00 0x00000fe0>, /* TI SCI DEBUG */
    			 <0x00 0x44860000 0x00 0x44860000 0x00 0x00040000>, /* SA3 sproxy config */
    			 <0x00 0x48000000 0x00 0x48000000 0x00 0x06408000>, /* DMSS */
    			 <0x00 0x60000000 0x00 0x60000000 0x00 0x08000000>, /* FSS0 DAT1 */
    			 <0x00 0x68000000 0x00 0x68000000 0x00 0x08000000>, /* PCIe0 DAT0 */
    			 <0x00 0x70000000 0x00 0x70000000 0x00 0x00040000>, /* OCSRAM */
    			 <0x00 0x78400000 0x00 0x78400000 0x00 0x00008000>, /* MAIN R5FSS0 ATCM */
    			 <0x00 0x78500000 0x00 0x78500000 0x00 0x00008000>, /* MAIN R5FSS0 BTCM */
    			 <0x00 0x7e000000 0x00 0x7e000000 0x00 0x00200000>, /* C7X_0 L2SRAM */
    			 <0x00 0x7e200000 0x00 0x7e200000 0x00 0x00200000>, /* C7X_1 L2SRAM */
    			 <0x01 0x00000000 0x01 0x00000000 0x00 0x00310000>, /* A53 PERIPHBASE */
    			 <0x05 0x00000000 0x05 0x00000000 0x01 0x00000000>, /* FSS0 DAT3 */
    			 <0x06 0x00000000 0x06 0x00000000 0x01 0x00000000>, /* PCIe0 DAT1 */
    			 
    			 ...

    J722S TRM:

    The window containing I2C4 is missing. Following is a patch to add it in:

    From 0b5a1e2d47ceec75cc7b6b65226e2b6ecd4b6767 Mon Sep 17 00:00:00 2001
    From: Jared McArthur <j-mcarthur@ti.com>
    Date: Tue, 29 Jul 2025 16:04:18 -0500
    Subject: [PATCH 1/1] arm64: dts: ti: k3-j722s: Add peripheral window in main
     CBASS memory map
    
    Signed-off-by: Jared McArthur <j-mcarthur@ti.com>
    ---
     arch/arm64/boot/dts/ti/k3-j722s.dtsi | 3 ++-
     1 file changed, 2 insertions(+), 1 deletion(-)
    
    diff --git a/arch/arm64/boot/dts/ti/k3-j722s.dtsi b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
    index 747f989a54a4..e8517bacefdc 100644
    --- a/arch/arm64/boot/dts/ti/k3-j722s.dtsi
    +++ b/arch/arm64/boot/dts/ti/k3-j722s.dtsi
    @@ -156,7 +156,8 @@ cbass_main: bus@f0000 {
     			 <0x00 0x0fd80000 0x00 0x0fd80000 0x00 0x00080000>, /* GPU */
     			 <0x00 0x0fd20000 0x00 0x0fd20000 0x00 0x00000100>, /* JPEGENC0_CORE */
     			 <0x00 0x0fd20200 0x00 0x0fd20200 0x00 0x00000200>, /* JPEGENC0_CORE_MMU */
    -			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Third peripheral window */
    +			 <0x00 0x0fe00000 0x00 0x0fe00000 0x00 0x000f0400>, /* Third peripheral window */
    +			 <0x00 0x20000000 0x00 0x20000000 0x00 0x0a008000>, /* Fourth peripheral window */
     			 <0x00 0x30040000 0x00 0x30040000 0x00 0x00080000>, /* PRUSS-M */
     			 <0x00 0x301C0000 0x00 0x301C0000 0x00 0x00001000>, /* DPHY-TX */
     			 <0x00 0x30101000 0x00 0x30101000 0x00 0x00080100>, /* CSI window */
    -- 
    2.34.1
    
    

    Best,
    Jared

  • Thanks Jared! This makes much more sense. I'll give it a try.

  • Hi Jared,

    Devices are able to communicate on i2c4 with this change, but I noticed the interrupt still may not be working right?
    I've removed all of my devices (All i2c4 ICs are depopulated from the board), but despite this, I still get slow response when using i2cdetect -r 5. The log prints this:

    omap_i2c fe80000.i2c: controller timed out

  • Hi Evan,

    I would expect the i2c4 to be slower, since the interrupt is routed through the gpiomux interrupt router instead of the GIC.

    Does the timeout occur every time, or is it sporadic?

    Best,
    Jared

  • Hi Jared,

    It's consistent. Every address that isn't connected causes the timeout.
    When I use this function on other i2c buses, the addresses without a device attached are fast to complete.

    When a device -is- attached, the i2cdetect completes for those addresses very quickly.

  • HI Evan,

    I see... That's interesting. I assume it has something to do with the gpiomux interrupt router, but I don't know what the issue is.

    I'll ask our development team if they have any knowledge.

    Best,
    Jared

  • Hi Evan,

    Does this version work? (taken from:  RE: AM67A: Enable i2c4 on AM67 ) 

    	main_i2c4: i2c@fe80000 {
    		compatible = "ti,am64-i2c", "ti,omap4-i2c";
    		reg = <0x00 0xfe80000 0x00 0x100>;
    		interrupts = <&main_gpio_intr 178 IRQ_TYPE_LEVEL_HIGH>;
    		#address-cells = <1>;
    		#size-cells = <0>;
    		power-domains = <&k3_pds 257 TI_SCI_PD_EXCLUSIVE>;
    		clocks = <&k3_clks 257 2>;
    		clock-names = "fck";
    	};

    Best,
    Jared

  • HI Jared,

    I tried it again and get the same response as before:

    omap_i2c fe80000.i2c: error -6: IRQ index 0 not found

    Perhaps we need interrupt-cells = <2> or <3>?

  • Hi Evan,

    Yeah, the main_gpio_intr has interrupt-cells = <1>, but changing that to <2> would likely cause issues with the preexisting child interrupts.

    Best,
    Jared

  • Should we try a different interrupt controller? I remember the datasheet listed a few others.

  • Hi Jared, I set the clock frequency in the dts to 1MHz, and it's still communicating at 400KHz, but it is no longer timing out?

  • Hi Evan,

    Should we try a different interrupt controller? I remember the datasheet listed a few others.

    I don't think the R5FSS0_CORE0 or MCU_R5FSS0_CORE0 routers have device-tree nodes.

    Hi Jared, I set the clock frequency in the dts to 1MHz, and it's still communicating at 400KHz, but it is no longer timing out?

    I saw that it was originally set to 100KHz, if you set it to 400KHz, does it work properly?

    Best,
    Jared

  • Hi Jared, No. 100KHz and 400KHz both cause some kind of delay on i2cdetect and invalid reads.

    I found that it's actually sending the addresses still at 400khz, but then does communicate at 1MHz.

  • Hi Evan,

    Interesting. I've raised a ticket internally, but for now, at least I2C4 is working.

    Best,
    Jared

  • Hi Evan,

    We were unable to recreate the timeout issue. The I2C4 works without issue on our EVM.

    Best,
    Jared

  • Hi Jared,

    That's good news, could you please confirm which version of SDK was used?

  • Hi Evan,

    The patch was applied to the 11.0 SDK.

    Best,
    Jared