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SK-AM62P-LP: how to config dss1 lvds to display

dongcan Zhi
Prodigy 70 points
Part Number: SK-AM62P-LP

Tool/software:

HI TI :

               I want to use the dss1 lvds  to display. How should the DTS be modified !

BR

 dongcan

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    Hi Divyansh ：

               I followed this guide to modify my dts.  tidss panel-simple probe ok ， but I couldn't measure the clock of dss1 old1 on the oscilloscope.

    BR

    dongcan

    /* dss1 oldi1 dts */

    &max9277_gmsl {
    status = "okay";

    ports {
    port@0 {
    lcd_in0: endpoint {
    remote-endpoint = <&oldi1_dss1_out>;
    };
    };
    };
    };


    &dss1 {
    status = "okay";
    assigned-clocks = <&k3_clks 235 7>,
    <&k3_clks 241 0>;
    assigned-clock-parents = <&k3_clks 235 9>, /* OLDI TX1 driven by PLL18 and DSS1 VP0 */
    <&k3_clks 241 1>; /* PLL18 for DSS1 VP0 */
    };

    &oldi1_dss1 {
    status = "okay";
    };

    &oldi1_dss1_ports {
    #address-cells = <1>;
    #size-cells = <0>;

    port@0 {
    reg = <0>;

    oldi1_dss1_in: endpoint {
    remote-endpoint = <&dss1_dpi0_out1>;
    };
    };

    port@1 {
    reg = <1>;

    oldi1_dss1_out: endpoint {
    remote-endpoint = <&lcd_in0>;
    };
    };
    };

    &dss1_ports {

    /* VP1: Output to OLDI */
    port@0 {
    reg = <0>;
    #address-cells = <1>;
    #size-cells = <0>;

    dss1_dpi0_out1: endpoint@0 {
    reg = <0>;
    remote-endpoint = <&oldi1_dss1_in>;
    };
    };
    };

    /* panel-simple.ko */

    static struct panel_desc gmsl_max9277 = {
    .timings = &gmsl_max9277_mode,
    .num_timings = 1,
    .bpc = 8,
    .size = {
    .width = 800,
    .height = 545,
    },
    .bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
    .bus_flags = DRM_BUS_FLAG_DE_HIGH,
    .connector_type = DRM_MODE_CONNECTOR_LVDS,
    };

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    Which SDK version are you using?

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    ti-processor-sdk-linux-am62pxx-evm-11.00.09.04

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    Please use 11.01.05.03, there is a related patch fix.

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    Hi  divyansh Mittal:

                I have updated the sdk to 11.01.05.03 , but this problem still exists.

               uname -r
               6.12.35-ge3e551586dfa-dirty

    BR

    dong can

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    Please share the following:

    devmem2 0x3020a160
kmsprint --device=/dev/dri/by-path/platform-30200000.dss-card
kmsprint --device=/dev/dri/by-path/platform-30220000.dss-card

kmstest --device=/dev/dri/by-path/platform-30200000.dss-card    #Share what you see on display/probe
kmstest --device=/dev/dri/by-path/platform-30220000.dss-card    #Share what you see on display/probe


    Can you please edit your previous response containing the DT and panel simple, and put it in a code block for better readability?

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    Fullscreen dss1.diff Download 
    diff --git a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
index ddcbdee85..9075f7ace 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
+++ b/arch/arm64/boot/dts/ti/k3-am62p5-sk.dts
@@ -218,16 +218,6 @@ sound_master: simple-audio-card,codec {
 		};
 	};
 
-	hdmi0: connector-hdmi {
-		compatible = "hdmi-connector";
-		label = "hdmi";
-		type = "a";
-		port {
-			hdmi_connector_in: endpoint {
-				remote-endpoint = <&sii9022_out>;
-			};
-		};
-	};
 };
 
 &main_gpio0 {
@@ -561,40 +551,6 @@ exp2: gpio@23 {
 				   "GPIO_eMMC_RSTn", "SoC_WLAN_SDIO_RST";
 	};
 
-	sii9022: bridge-hdmi@3b {
-		compatible = "sil,sii9022";
-		reg = <0x3b>;
-		interrupt-parent = <&exp1>;
-		interrupts = <16 IRQ_TYPE_EDGE_FALLING>;
-		#sound-dai-cells = <0>;
-		sil,i2s-data-lanes = < 0 >;
-
-		hdmi_tx_ports: ports {
-			#address-cells = <1>;
-			#size-cells = <0>;
-
-			/*
-			 * HDMI can be serviced with 3 potential VPs -
-			 * (DSS0 VP1 / DSS1 VP0 / DSS1 VP1).
-			 * For now, we will service it with DSS0 VP1.
-			 */
-			port@0 {
-				reg = <0>;
-
-				sii9022_in: endpoint {
-					remote-endpoint = <&dss0_dpi1_out>;
-				};
-			};
-
-			port@1 {
-				reg = <1>;
-
-				sii9022_out: endpoint {
-					remote-endpoint = <&hdmi_connector_in>;
-				};
-			};
-		};
-	};
 };
 
 &main_i2c2 {
@@ -841,6 +797,13 @@ AM62PX_MCU_IOPAD(0x028, PIN_OUTPUT, 0)	/* (D7) WKUP_UART0_TXD */
 		>;
 		bootph-all;
 	};
+	mcu_uart0_pins_default: mcu-uart0-default-pins {
+	pinctrl-single,pins = <
+			AM62PX_MCU_IOPAD(0x0014, PIN_INPUT, 0)	/* (B6) /* MCU_UART0_RXD */
+			AM62PX_MCU_IOPAD(0x0018, PIN_OUTPUT, 0)	/* (C8) /* MCU_UART0_TXD */
+		>;
+		bootph-all;
+	};
 };
 
 &wkup_uart0 {
@@ -851,6 +814,13 @@ &wkup_uart0 {
 	bootph-all;
 };
 
+&mcu_uart0 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&mcu_uart0_pins_default>;
+	status = "okay";
+	bootph-all;
+};
+
 /* mcu_gpio0 and mcu_gpio_intr are reserved for mcu firmware usage */
 &mcu_gpio0 {
 	status = "reserved";
@@ -863,7 +833,67 @@ &mcu_gpio_intr {
 &dss_oldi_io_ctrl {
 	bootph-all;
 };
+&max9277_gmsl {
+	status = "okay";
 
+		ports {
+			port@0 {
+				lcd_in0: endpoint {
+					remote-endpoint = <&oldi1_dss1_out>;
+			};
+		};
+	};
+};
+
+
+&dss1 {
+	status = "okay";
+	assigned-clocks = <&k3_clks 235 7>,
+	<&k3_clks 241 0>;
+	assigned-clock-parents = <&k3_clks 235 9>, /* OLDI TX1 driven by PLL18 and DSS1 VP0 */
+	<&k3_clks 241 1>; /* PLL18 for DSS1 VP0 */
+};
+
+&oldi1_dss1 {
+	status = "okay";
+};
+
+&oldi1_dss1_ports {
+	#address-cells = <1>;
+	#size-cells = <0>;
+
+	port@0 {
+		reg = <0>;
+
+		oldi1_dss1_in: endpoint {
+			remote-endpoint = <&dss1_dpi0_out1>;
+		};
+	};
+
+	port@1 {
+		reg = <1>;
+
+		oldi1_dss1_out: endpoint {
+			remote-endpoint = <&lcd_in0>;
+		};
+	};
+};
+
+&dss1_ports {
+
+	/* VP1: Output to OLDI */
+	port@0 {
+		reg = <0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		dss1_dpi0_out1: endpoint@0 {
+			reg = <0>;
+			remote-endpoint = <&oldi1_dss1_in>;
+		};
+	};
+};
+#if 0
 &dss0 {
 	bootph-all;
 	status = "okay";
@@ -881,6 +911,7 @@ dss0_dpi1_out: endpoint {
 		};
 	};
 };
+#endif
 
 &epwm0 {
 	/* Pin 24/26 of J4 */
diff --git a/drivers/gpu/drm/panel/panel-simple.c b/drivers/gpu/drm/panel/panel-simple.c
index cc05e4367..5b58de2a5 100644
--- a/drivers/gpu/drm/panel/panel-simple.c
+++ b/drivers/gpu/drm/panel/panel-simple.c
@@ -2923,6 +2923,32 @@ static const struct panel_desc lg_lb070wv8 = {
 	.connector_type = DRM_MODE_CONNECTOR_LVDS,
 };
 
+static struct display_timing gmsl_max9277_mode = {
+	.pixelclock = {26160000,26160000,26160000},
+	.hactive = {256,256,256},
+	.hfront_porch = {403,403,403},
+	.hback_porch = {45,45,45},
+	.hsync_len = {96,96,96},
+	.vactive = {64,64,64},
+	.vfront_porch = {415,415,415},
+	.vback_porch = {3,3,3},
+	.vsync_len = {63,63,63},
+};
+
+static struct panel_desc gmsl_max9277 = {
+	.timings = &gmsl_max9277_mode,
+	.num_timings = 1,
+	.bpc = 8,
+	.size = {
+		.width = 800,
+		.height = 545,
+	},
+	.bus_format = MEDIA_BUS_FMT_RGB888_1X7X4_SPWG,
+	// .bus_flags = DRM_BUS_FLAG_DE_HIGH | DRM_BUS_FLAG_PIXDATA_SAMPLE_NEGEDGE,
+	.bus_flags = DRM_BUS_FLAG_DE_HIGH,
+	.connector_type = DRM_MODE_CONNECTOR_LVDS,
+};
+
 static const struct drm_display_mode lincolntech_lcd185_101ct_mode = {
 	.clock = 155127,
 	.hdisplay = 1920,
@@ -4780,7 +4806,12 @@ static const struct of_device_id platform_of_match[] = {
 	}, {
 		.compatible = "edt,etm043080dh6gp",
 		.data = &edt_etm043080dh6gp,
-	}, {
+	}, 
+		{
+		.compatible = "maxim,max9277",
+		.data = &gmsl_max9277,
+	},
+		{
 		.compatible = "edt,etm0430g0dh6",
 		.data = &edt_etm0430g0dh6,
 	}, {
    This is my diff

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points 

     kmsprint --device=/dev/dri/by-path/platform-30220000.dss-card
Connector 0 (41) LVDS-1 (connected)
  Encoder 0 (40) NONE
    Crtc 0 (39) 256x64@60.00 26.160 256/403/96/45/? 64/415/63/3/? 60 (60.00) 0x0 0x48


     kmstest --device=/dev/dri/by-path/platform-30220000.dss-card
Connector 0/@41: LVDS-1
  Crtc 0/@39: 256x64@60.00 26.160 256/403/96/45/? 64/415/63/3/? 60 (60.00) 0x0 0x48
  Plane 0/@32: 0,0-256x64
    Fb 49 256x64-XR24
press enter to exit

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points 

    devmem2 0x3020a160
/dev/mem opened.
[  667.585644] audit: type=1701 audit(1736660868.476:47): auid=4294967295 uid=0 gid=0 ses=4294967295 subj=kernel pid=7170 comm="devmem2" exe="/usr/bin/devmem2" sig=7 res=1
Memory mapped at address 0xffff83811000.
[  667.610694] audit: type=1334 audit(1736660868.504:48): prog-id=32 op=LOAD
[  667.617570] audit: type=1334 audit(1736660868.508:49): prog-id=33 op=LOAD
[  667.624415] audit: type=1334 audit(1736660868.516:50): prog-id=34 op=LOAD
Bus error (core dumped)

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    What happens when you set status of Dss0 to "okay"
    Are you then able to read 0x3020a160?
    If you are able to read, does the display work?

  • 0 in reply to Divyansh Mittal
    TI__Expert 7640 points

    Hi,
    I just checked on my end. I am able to get signals when configuring only OLDI TX1 and not TX0.
    It is weird not reading 3020a160 is giving error to you, this is not the case on my setup.

    Can you also read 0x3022a160?

    You my try my reference implementation configuring a different panel to see if you are at least seeing data on the lines:

    // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
/**
 * Rocktech Panel (single-link lvds) with AM62P-SK EVM in independent mode
 *
 * AM62P-SKEVM: https://www.ti.com/tool/SK-AM62P-LP
 *
 * Copyright (C) 2024 Texas Instruments Incorporated - http://www.ti.com/
 */

/dts-v1/;
/plugin/;

#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h>

&{/} {
	display0 {
		compatible = "rocktech,rk101ii01d-ct", "panel-simple";

		port {
			lcd0_in: endpoint {
				remote-endpoint = <&oldi1_dss1_out>;
			};
		};
	};
};

&dss1 {
	status = "okay";
    assigned-clocks = <&k3_clks 235 7>,
                      <&k3_clks 241 0>;
	assigned-clock-parents = <&k3_clks 235 9>, /* OLDI TX1 driven by PLL18 and DSS1 VP0 */
                            <&k3_clks 241 1>;  /* PLL18 for DSS1 VP0 */
};

&oldi1_dss1 {
	status = "okay";	
};

&oldi1_dss1_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;

		oldi1_dss1_in: endpoint {
			remote-endpoint = <&dss1_dpi0_out1>;
		};
	};

	port@1 {
		reg = <1>;

		oldi1_dss1_out: endpoint {
			remote-endpoint = <&lcd0_in>;
		};
	};
};

&dss1_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	/* DSS1 VP1: Output to OLDI1 */
	port@0 {
		reg = <0>;

		dss1_dpi0_out1: endpoint {
			remote-endpoint = <&oldi1_dss1_in>;
		};
	};
};

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    [ 100.428365] [drm] Initialized tidss 1.0.0 for 30200000.dss on minor 0
    [ 114.512253] [drm] Initialized tidss 1.0.0 for 30220000.dss on minor 1

    When I set status of Dss0 to "okay", I still can't read 0x3020a160

    DTS config

    &max9277_gmsl {
	status = "okay";

		ports {
			port@0 {
				lcd_in0: endpoint {
					remote-endpoint = <&oldi1_dss1_out>;
			};
		};
	};
};

&dss1 {
	status = "okay";
	assigned-clocks = <&k3_clks 235 7>,
	<&k3_clks 241 0>;
	assigned-clock-parents = <&k3_clks 235 9>, /* OLDI TX1 driven by PLL18 and DSS1 VP0 */
	<&k3_clks 241 1>; /* PLL18 for DSS1 VP0 */
};

&dss0 {
	bootph-all;
	status = "okay";
	pinctrl-names = "default";
	pinctrl-0 = <&main_dpi_pins_default>;
};

&oldi1_dss1 {
	status = "okay";
};

&oldi1_dss1_ports {
	#address-cells = <1>;
	#size-cells = <0>;

	port@0 {
		reg = <0>;

		oldi1_dss1_in: endpoint {
			remote-endpoint = <&dss1_dpi0_out1>;
		};
	};

	port@1 {
		reg = <1>;

		oldi1_dss1_out: endpoint {
			remote-endpoint = <&lcd_in0>;
		};
	};
};

&dss1_ports {

	/* VP1: Output to OLDI */
	port@0 {
		reg = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		dss1_dpi0_out1: endpoint@0 {
			reg = <0>;
			remote-endpoint = <&oldi1_dss1_in>;
		};
	};
};

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    OK Let me try..

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    Not able to read that register is very weird to me. Is there some kind of firewall you've setup to prevent read in your software application?
    If you have TI EVM, would recommend checking if the panel works there with our dts.

    Since devmem2 is not working, can you try reading that register through another core via CCS?

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    If I use dss0 odli0 alone, the registers"0x3020a160" can be read, after my days off I will try it on the ti evm board, thanks a lot bro！

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    Hi Divyansh ：

      if I use Ti EVM ， follow your dts ，  It's normal.

    BR 

    Dong Can

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    With the same dts, 
    1. Can you read 0x3020a160 and 0x3022a160?
    2. What happens when you replace 'rocktech' panel compatible with your panel compatible?

  • 0 in reply to Divyansh Mittal
    Prodigy 70 points

    Hi Divyansh:

                 1、yes， I can read  with EVM

                 2、clk was measured

          Perhaps there is a problem with the hardware of the dss1 module of my custom board. By the way , how to enbale dss0 dual output synchronously with dpi and lvds? I used the dpi and lvds functions of dss0 respectively, and they worked normally.  Here is another question of mine . SK-AM62P-LP: how to enbale dss0 dual output synchronously with dpi and lvds? - Processors forum - Processors - TI E2E support forums

    Thanks 

    Dong Can

  • 0 in reply to dongcan Zhi
    TI__Expert 7640 points

    Yes, this most likely depicts issue on your custom board, especially since you are not able to access those registers.
    Will respond to the other thread.