TMS320C6657: How can i prepare the boot file from out file for dual core?

#include <stdio.h>
#include <stdint.h>
#include <string.h>

#include "ti/csl/csl_chip.h"
#include "ti/csl/csl_cacheAux.h"
#define KICK0 ( *(volatile uint32_t *)0x02620038 )
#define KICK1 ( *(volatile uint32_t *)0x0262003C )
#define KICK0_UNLOCK 0x83E70B13
#define KICK1_UNLOCK 0x95A4F1E0

// now safe to write to protected registers like BOOTCFG

// Core1 wake-up constants
#define BOOT_MAGIC_ADDR       (*(volatile uint32_t*)0x87FFFCU)
#define CORE1_BOOT_ADDR       0x00800000U
#define IPCGR1                (*(volatile uint32_t *)0x02620244U)
#define IPCAR1                (*(volatile uint32_t *)0x02620284U)

// Shared memory setup
#define SHARED_MEM_BASE       0x0C000000
#define SHARED_MEM_OFFSET     2700
#define SHARED_MEM_ADDR       (SHARED_MEM_BASE + SHARED_MEM_OFFSET)
#define BUFFER_SIZE           4096

typedef struct {
    volatile uint32_t flag;
    volatile uint32_t size;
    volatile char buffer[BUFFER_SIZE];
} SharedPacket;

volatile SharedPacket* shared = (SharedPacket*)SHARED_MEM_ADDR;

void short_delay() {
    volatile int i;
    for (i = 0; i < 100000; i++) {}
}

// ------------- Core0 Functions -------------

void wakeUpCore1() {
    BOOT_MAGIC_ADDR = CORE1_BOOT_ADDR;  // Core1 entry point in L2SRAM
    IPCGR1 = 1;                          // Trigger Core1
}

void sendFromCore0(uint32_t id) {
    shared->size = snprintf((char*)shared->buffer, BUFFER_SIZE, "Hello from CORE0: msg %u", id);
    shared->flag = 0xA5A50000 | (id & 0xFFFF);
    CACHE_wbL1d((void*)shared, sizeof(SharedPacket), CACHE_WAIT);
    IPCGR1 = 1;
    printf("[C66xx_0] Sent msg %u: \"%s\"\n", id, shared->buffer);
}

void waitReplyCore0() {
    while (1) {
        CACHE_invL1d((void*)shared, sizeof(SharedPacket), CACHE_WAIT);
        if (shared->flag == 0) break;
        short_delay();
    }
    printf("[C66xx_0] Got reply: \"%s\"\n", shared->buffer);
}

// ------------- Core1 Functions -------------

void handleCore1() {
    CACHE_invL1d((void*)shared, sizeof(SharedPacket), CACHE_WAIT);
    if (shared->flag != 0) {
        uint32_t msgId = shared->flag & 0xFFFF;
        printf("[C66xx_1] Got msg %u: \"%s\"\n", msgId, shared->buffer);

        snprintf((char*)shared->buffer, BUFFER_SIZE, "CORE1 ACK: msg %u", msgId);
        shared->size = strlen((char*)shared->buffer);
        shared->flag = 0;
        CACHE_wbL1d((void*)shared, sizeof(SharedPacket), CACHE_WAIT);
    }
}

// ------------- Entry Point (both cores) -------------

void main() {
    uint32_t coreNum = CSL_chipReadReg(CSL_CHIP_DNUM);
    KICK0 = KICK0_UNLOCK;
    KICK1 = KICK1_UNLOCK;
    if (coreNum == 0) {
        // ---------- Core0 ----------
        printf("[C66xx_0] CORE0 starting...\n");

        wakeUpCore1();  // Boot Core1 from L2SRAM

        uint32_t count = 0;
        while (1) {
            sendFromCore0(count);
            waitReplyCore0();
            count++;
            short_delay();
        }

    } else if (coreNum == 1) {
        // ---------- Core1 ----------
        printf("[C66xx_1] CORE1 waiting...\n");

        while (1) {
            IPCAR1 = 1;  // Acknowledge IPC
            handleCore1();
            short_delay();
        }
    }

    while (1);  // Never exit
}