Tool/software:
Hello,
Background is as below,
1)initially we enable interrupt by enabling bit in specific register(here in TI, we call it VIM)
2)During critical sections, we disable interrupt and enable again after critical section execution is done.
3)In worst case, say exactly during critical section only, if interrupt occurs, off-course it will not be served(no isr execution) at that instant as interrupt is disabled but this will set pending bit so once we enable interrupt(after critical section execution), at that time only, isr will be executed.
So, query is, We will not actually loose serving of interrupt(in worst case mentioned above) but it is just post -pone of serving of interrupt, correct?
Regards,
Akshay
