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AM62P-Q1: PCB material for LPDDR4 usage

liujian zhang
Prodigy 250 points
Part Number: AM62P-Q1

Tool/software:

Hello,

for AM62P54  LPDDR4 3200Mbps, the std PCB material is OK or need higher frequency material? and what's the restriction?

thanks!

  • 0
    TI__Guru* 86330 points

    Yes, standard PCB material can be used.  Please follow the guidelines here: https://www.ti.com/lit/pdf/sprad66

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 250 points

    Hello 

    some questions as below, pls help to reply, thanks!

            Impedance control for LPDDR4: as TI guideline, LPDDR4 point to point signals should be routed as single end 40R, all signals should be routed in inner layer, and also keep signal space as 3w rule

    Questions:

    1. Whether we could change these point to point signals from single end 40R to single end 46R or 50R or not?
    2. 3W rule is too large for us to follow considering our PCB size, whether we could change the rule as 2W (center to center) or not?
    3. If some signals routed in outer layer, whether there is some risk or not?
    1. T-Branch: as only one LPDDR4 interface been used in the design, whether this T-Branch design could be ignore or not? fly-by topology is applicable or not?
  • 0 in reply to liujian zhang
    TI__Guru* 86330 points

    1. yes these can be increased

    2. Yes, but i would recommend board simulation to ensure no intersymbol interference or crosstalk

    3. Signal can be routed on outer layer, but again, i would recommend board simulations.  Ensure proper ground references for those layers, proper impedance matching, and keep propagation delay matching as specified in the app note.

    If you only have one LPDDR4 device, you won't need to do any T-branching of DQ signals. Multiple LPDDR4 devices is not supported.  

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 250 points

    Hello,

    thanks for reply, i have additional question regarding T-branching,  as below show, for CA lines, does need T-branching? or fly-by topology is applicable? or any recommendation? 

    thanks!

    below is the screenshot from "AM62Ax, AM62Px, AM62Dx LPDDR4 Board Design and Layout Guidelines", do CA lines need to follow below rules? Here i want confirm with you.

  • 0 in reply to liujian zhang
    TI__Guru* 86330 points

    Yes, T-branching is required for the CA lines.  Please follow the guidelines in the app note.  Fly-by topology is not allowed.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 250 points

    Hello James,

    thanks!

    additional question,  for different ranks,  if the data line( for example: DQ1 and DQ10) need to do skew match? 

  • 0 in reply to liujian zhang
    TI__Guru* 86330 points

    This is detailed in the app note.  DQx and all associated DQSx DM signals within a byte need to be skew matched according to the app note.  Skew matching is not necessary across different data bytes.

    Regards,

    James