I have been looking through the keystone training and the sprugy5a user guide on the bootloader and had a few questions that needed clarification.
A little background: We will be making use of either SRIO or Ethernet to boot multiple DSPs by broadcasting or using point-to-point from a host processor on the same card. All of the cores are expected to run the same image which will load into SL2 and DDR3. At run time, different cores and DSPs may run different portions of the codebase depending on applications etc. Individual core L2s will only contain data.
My questions are:
The bootloader in ROM allocates a portion of corePac0 L2 for its use. These values include a DDR configuration table and the boot parameter tables. The user guide talks of the DDR config table values being all zero by default in the L2 space. Since the bootcode is in ROM, we obviously cannot change that from its default setup. Does the setup for the DDR work as follows: Bootloader runs with mode setup as SRIO or Ethernet; host then sends DDR table configuration code via a boot table over SRIO or Ethernet; on completion corePac0 jumps to DDR table configuration code (in corePac0 L2); code reset BOOT_MAGIC address to null and then populates entries in DDR config table then host after waiting a while to ensure that DSP has completed initialization loads application code similarly via SRIO or Ethernet using boot tables then writes the start address into the core 0 magic address which starts application. This idea can also be used to setup the EMAC mode boot parameter tables such as MAC addresses, ports etc to use for Ethernet packets directed to the PAs for each DSP. I am a little unsure about how the packets get to the DSP over Ethernet before the Ethernet mode boot parameter table values are setup in L2 space since the default values are all zeros so than the MAC address for the DSP will be all zeros so how will the host device know the mac address to send the Ethernet packets to?
The SRIO example under mcsdk_2_00_02_14\tools\boot_loader\examples\srio\ is really for DSP to DSP srio transfer in Direct I/o mode ? Can a non-DSP host also make use of it as long as it knows the destination memory space layout?
Is the corePacs BOOT_MAGIC_ADDRESS all intialized to zeros at initialization? I assume so as this location is being sampled to see a non-zero value to indicate that boot has completed and can then use that address as the start address for each corePac. I am assuming that the start address which is the first word in the boot table will be written after the termination record is received.
We should only need one bootload per DSP as all code is in SL2 and DDR3. The SL2 starting code is also tasked with setting up the boot magic addresses for the other cores and should write to the IPC register to trigger interrupts for each secondary corePac.
Can you confirm: For the SRIO mode, the SRIO message (i.e. boot tables sections which itself are prepended with the magic address) is prepended with the 32bit SRIO message mode boot header. While for the Ethernet boot mode the 32bit boot table frame header (which has the boot magic number) prepends the boot table sections but the Ethernet header prepends that.
The Ethernet ready frame that is configurable to be sent by the DSP every 3 seconds stops sending when the Rx queue receives the first boot packet. Also the user guide talks about after configuration of PA etc. is complete that the Ethernet ready frame is then sent. My question then is that if the bootloader is in Ethernet mode, it will run configuration so how can one setup the configuration. I am guessing this cannot be done in Ethernet mode and maybe this has to be done in SRIO mode prior to using Ethernet mode.
