Tool/software:
I use a DRA829J-Q1 supplied with two PMIC according PDN-0C on my HW.
At Startup, PORz_out (green) is driven high before MCU_PORz (deep blue) is released by PMIC.
light blue: MCU_RESETSTATz
purple: RESETSTATz
My expectation would be PORz_out going high 1500ns after MCU_PORz as stated in SPRSP35K table 6-8.
What can be the reason for the previous pulse? Is this a critical behaviour, as only usage of PORz_out in my HW is disabling Bootmode buffers similar to EVM?
Regards, Peter
The SoC's PORz_OUT is a buffered output of the PORz input signal per TRM's Table 5-2422.
(DM Note: The Dual Leo PMIC PDN-0C implements an Isolated MCU & Main power routing scheme, therefore Table-17 & Fig 6-12 are the correct reference. Table 6-16 & Fig 6-11 should not be used since they describe reset signals for "Combined MUC and Main Domain" PDN schemes.)
The signal connected to PORz input is "SOC_PORz_1V8" that is sourced from PMIC-A's GPIO11. This is an open-drain output pulled up to PMIC sourced power rail VDA_MCU_1V8 which is enabled at 1.7ms into power up seq. Both PORz & SOC_PORz_1V8 signals are held low during power up seq and are released/set high at the end of the power up seq at 12.7ms. The scope shot shows the pulse on PORz_OUT (SOC_PORz_1V8) to be driven low at ~11ms before MCU_PORz is set high at the end of the power up seq. It appears this pulse PORz_OUT pulse is occurring before the SOC_PORz_1V8's open-drain supply VDA_MCU_1V8 is enabled at 1.7ms. Any modulations of prior to enabling of the open-drain reference voltage should be ignored since the SOC_PORz_1V8 signal is not fully activated.
This should not impact latching of bootmode settings into the SoC. Typically our J7xxx EVMs will use MCU_RESETSTATz signal to control bootmode buffer since it is SoC's internal MCU reset release signal.
Hi Bill, thanks for the answer.
I did a further measurement which shows that the high pulse occurs after VDA_MCU_1V8 is fully powered.
dark blue: PMIC A GPIO11, with pullup to VDA_MCU_1V8
light blue: same signal after a schmitt trigger gate, supplied with VDA_MCU_1V8
purple: PORz_out
green: VDA_MCU_1V8
So for me it´s still not clear where this PORz_out high pulse is coming from, as the only driver is the Jacinto itself.
I also suppose there is no impact on latching of bootmode settings as these are driven again by HW during the second low phase of PORz_out, and should be captured correctly with the second rising edge of PORz_out. Or do you see a necessity to search deeper for the root cause of the pulse which occurs after enabling of the open-drain reference voltage contrary to you assumption before.
Regards, Peter
