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AM4372: Pull-up/down resistor

Part Number: AM4372

Tool/software:

Hi team,

Could you answer the following about IO pins specification of the AM4372?

1. Regarding to the pins which have internal pull-up/down resistors, Could you tell me the resistance of them?
2. Are there any recommendations for implementing external pull-up/pull-down resistors in GPIOs?

Best regards,
Goto

  • Hello Goto,

    Thank you for the query.

    Data sheet reference

    DC Electrical Characteristics (continued)

    All other LVCMOS pins (VDDSHVx = 1.8 V; x=1–11)

    All other LVCMOS pins (VDDSHVx = 3.3 V; x=1–11)

    The customer needs to consider the combined worst case leakage current associated with all devices connected to a signal to understand what value external pull is required to ensure the resulting potential remains at a valid high or low logic level when not actively driven to a high or low logic level.  They need to be careful and not use a resistor value that is too low, such that the output buffer driving the signal is not able to achieve a valid logic state.  They may also need to consider noise sources that could induce a potential on a signal and make sure they apply an appropriate external pull that is able to hold a valid logic level when exposed to the noise source. 

    Regards,

    Sreenivasa

  • Hello Goto,

    The below tips can be used as reference:

    https://www.ti.com/lit/ds/symlink/omap-l138.pdf

    4.3 Pullup/Pulldown Resistors

    Tips for choosing an external pullup/pulldown resistor:
    • Consider the total amount of current that may pass through the pullup or pulldown resistor. Make sure
    to include the leakage currents of all the devices connected to the net, as well as any internal pullup or
    pulldown resistors.
    • Decide a target value for the net. For a pulldown resistor, this should be below the lowest VIL level of
    all inputs connected to the net. For a pullup resistor, this should be above the highest VIH level of all
    inputs on the net. A reasonable choice would be to target the VOL or VOH levels for the logic family of
    the limiting device; which, by definition, have margin to the VIL and VIH levels.
    • Select a pullup/pulldown resistor with the largest possible value; but, which can still ensure that the net
    will reach the target pulled value when maximum current from all devices on the net is flowing through
    the resistor. The current to be considered includes leakage current plus, any other internal and
    external pullup/pulldown resistors on the net.
    • For bidirectional nets, there is an additional consideration which sets a lower limit on the resistance
    value of the external resistor. Verify that the resistance is small enough that the weakest output buffer
    can drive the net to the opposite logic level (including margin).
    • Remember to include tolerances when selecting the resistor value.
    • For pullup resistors, also remember to include tolerances on the IO supply rail.
    • For most systems, a 1-kΩ resistor can be used to oppose the IPU/IPD while meeting the above
    criteria. Users should confirm this resistor value is correct for their specific application.
    • For most systems, a 20-kΩ resistor can be used to compliment the IPU/IPD on the boot and
    configuration pins while meeting the above criteria. Users should confirm this resistor value is correct
    for their specific application.
    • For more detailed information on input current (II
    ), and the low-/high-level input voltages (VIL and VIH)
    for the device, see Section 5.3, Recommended Operating Conditions.
    • For the internal pullup/pulldown resistors for all device pins, see the peripheral/system-specific terminal
    functions table.

    Regards,

    Sreenivasa

  • Hello Goto,

    Expert input regarding selection of pullup value:

    We are not expecting any issue as long as the steady-state voltage applied to the input of an IO cell is less than VIL or greater than VIH.

    Regards,

    Sreenivasa