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TDA4VEN-Q1: linux & mcu2_0 gpio Interrupt the conflict

cesar.xu
Intellectual 370 points
Part Number: TDA4VEN-Q1

Tool/software:

Hi,

mcu20 requires the use of 191 and 192 banks Interrupt

However, due to the occupation of linux, after attempting to modify it now,

the linux gpio cannot be used, please fix my modification.

	main_gpio_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <3>;
		ti,interrupt-ranges = <0 32 1>, <3 35 3>;  // 190,193-195
	};

	main_gpio1_intr: interrupt-controller@a00000 {
		compatible = "ti,sci-intr";
		reg = <0x00 0x00a00000 0x00 0x800>;
		ti,intr-trigger-type = <1>;
		interrupt-controller;
		interrupt-parent = <&gic500>;
		#interrupt-cells = <1>;
		ti,sci = <&dmsc>;
		ti,sci-dev-id = <3>;
		ti,interrupt-ranges = <0 38 6>;
	};

	main_gpio0: gpio@600000 {
		compatible = "ti,am64-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00600000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio_intr>;
		interrupts = <190>, /* <191>, <192>, */
			     <193>, <194>, <195>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 77 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 77 0>;
		clock-names = "gpio";
	};

	main_gpio1: gpio@601000 {
		compatible = "ti,am64-gpio", "ti,keystone-gpio";
		reg = <0x00 0x00601000 0x00 0x100>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-parent = <&main_gpio1_intr>;
		interrupts = <180>, <181>, <182>,
			     <183>, <184>, <185>;
		interrupt-controller;
		#interrupt-cells = <2>;
		ti,davinci-gpio-unbanked = <0>;
		power-domains = <&k3_pds 78 TI_SCI_PD_EXCLUSIVE>;
		clocks = <&k3_clks 78 0>;
		clock-names = "gpio";
	};

log:

    1.624724] am65-cpsw-nuss 8000000.ethernet: initializing am65 cpsw nuss version 0x6BA01903, cpsw version 0x6BA81903 Ports: 3 quirks:00000006
[    1.637795] am65-cpsw-nuss 8000000.ethernet: initialized cpsw ale version 1.5
[    1.644929] am65-cpsw-nuss 8000000.ethernet: ALE Table size 512, Policers 32
[    1.652674] am65-cpsw-nuss 8000000.ethernet: CPTS ver 0x4e8a010d, freq:500000000, add_val:1 pps:0
[    1.670756] am65-cpsw-nuss 8000000.ethernet: set new flow-id-base 19
[    1.685140] mmc0: CQHCI version 5.10
[    1.686231] davinci_gpio 600000.gpio: error -ENXIO: IRQ index 4 not found
[    1.700980] clk: Disabling unused clocks
[    1.710242] PM: genpd: Disabling unused power domains
[    1.715397] ALSA device list:
[    1.718435]   No soundcards found.
[    1.735577] mmc0: SDHCI controller on fa10000.mmc [fa10000.mmc] using ADMA 64-bit
[    1.743279] Waiting for root device PARTUUID=d73bf4db-02...
[    1.865975] mmc0: Command Queue Engine enabled
[    1.870454] mmc0: new HS200 MMC card at address 0001
[    1.876838] mmcblk0: mmc0:0001 A8A398 7.28 GiB
[    1.883008]  mmcblk0: p1 p2 p3 p4 < p5 p6 >
[    1.888283] mmcblk0boot0: mmc0:0001 A8A398 4.00 MiB
[    1.894148] mmcblk0boot1: mmc0:0001 A8A398 4.00 MiB
[    1.899917] mmcblk0rpmb: mmc0:0001 A8A398 4.00 MiB, chardev (239:0)
[   11.785463] i2c 0-0048: deferred probe pending: i2c: supplier 600000.gpio not ready
[   11.793148] platform fa00000.mmc: deferred probe pending: platform: supplier regulator-TLV71033 not ready
[   11.802702] platform regulator-TLV71033: deferred probe pending: platform: supplier 600000.gpio not ready
[   11.812253] platform 2b300050.target-module: deferred probe pending: (reason unknown)

Regards,

Cesar

  • 0
    TI__Mastermind 19370 points

    Hi Cesar,

    I am looking into this and speaking to the team. I will get back to you.

    Thanks,

    Neehar

  • 0 in reply to Semon Zhang
    Intellectual 370 points

    Hi Semon,

    These materials cannot solve the current problem. Please confront the current issue directly.

    Regards,

    Cesar

  • 0 in reply to cesar.xu
    TI__Expert 8551 points
    cesar.xu said:
    hese materials cannot solve the current problem. Please confront the current issue directly.

    Hi Cesar

        please refer to this change, I test it on EVM, Linux can bring up,

        then the left GPIO interrupt can be used for RTOS, for GPIO0: 193-195, GPIO1: 183-185

        --------------------------------

       

    Fullscreen dts-gpio-chng.diff Download 
    diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index bec036b2a..4dff3ca47 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -193,6 +193,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-microtips-mf101hie-panel.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-pwm.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-vision-apps.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-edgeai-apps.dtbo
 
 # Boards with J784s4 SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
index 3e5ca8a3e..d538843e3 100644
--- a/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am62p-j722s-common-main.dtsi
@@ -557,8 +557,7 @@ main_gpio0: gpio@600000 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <190>, <191>, <192>,
-			     <193>, <194>, <195>;
+		interrupts = <190>, <191>, <192>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		ti,davinci-gpio-unbanked = <0>;
@@ -573,8 +572,7 @@ main_gpio1: gpio@601000 {
 		gpio-controller;
 		#gpio-cells = <2>;
 		interrupt-parent = <&main_gpio_intr>;
-		interrupts = <180>, <181>, <182>,
-			     <183>, <184>, <185>;
+		interrupts = <180>, <181>, <182>;
 		interrupt-controller;
 		#interrupt-cells = <2>;
 		ti,davinci-gpio-unbanked = <0>;
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index e362bfbb6..82e5180da 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -170,7 +170,7 @@ vdd_sd_dv: regulator-TLV71033 {
 		regulator-max-microvolt = <3300000>;
 		regulator-boot-on;
 		vin-supply = <&vsys_5v0>;
-		gpios = <&main_gpio0 70 GPIO_ACTIVE_HIGH>;
+		gpios = <&main_gpio0 29 GPIO_ACTIVE_HIGH>;
 		states = <1800000 0x0>,
 			 <3300000 0x1>;
 	};
@@ -469,6 +469,10 @@ &cpsw_port1 {
 	status = "okay";
 };
 
+&main_gpio0 {
+	status = "okay";
+};
+
 &main_gpio1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index d3411f80c..67b0eef84 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -474,12 +474,12 @@ main_pmx0_range: gpio-range {
 &main_gpio0 {
 	gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
 			<&main_pmx0 70 72 17>;
-	ti,ngpio = <87>;
+	ti,ngpio = <32>;
 };
 
 &main_gpio1 {
 	gpio-ranges = <&main_pmx0 7 101 25>, <&main_pmx0 42 137 5>,
 			<&main_pmx0 47 143 3>, <&main_pmx0 50 149 2>;
 	gpio-reserved-ranges = <0 7>, <32 10>;
-	ti,ngpio = <73>;
+	ti,ngpio = <32>;
 };
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1429e8c02..dbd110260 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # generic gpio support: platform drivers, dedicated expander chips, etc
-
+EXTRA_CFLAGS += -DDEBUG
 ccflags-$(CONFIG_DEBUG_GPIO)	+= -DDEBUG
 
 obj-$(CONFIG_GPIOLIB)		+= gpiolib.o
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index f2cc94c26..66595c31f 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -162,7 +162,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 	struct davinci_gpio_controller *chips;
 	struct device *dev = &pdev->dev;
 	struct device_node *dn = dev_of_node(dev);
-
+printk("%s %d, nirq %d\n", __FUNCTION__,__LINE__, nirq);
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
 	 * and "ngpio" is one more than the largest zero-based
@@ -188,11 +188,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 		nirq = gpio_unbanked;
 	else
 		nirq = DIV_ROUND_UP(ngpio, 16);
-
-	if (nirq > MAX_INT_PER_BANK) {
-		dev_err(dev, "Too many IRQs!\n");
-		return -EINVAL;
-	}
+printk("%s %d, ngpio %d, nirq %d\n", __FUNCTION__,__LINE__, ngpio, nirq);
 
 	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
 	if (!chips)
@@ -204,6 +200,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 
 	for (i = 0; i < nirq; i++) {
 		chips->irqs[i] = platform_get_irq(pdev, i);
+		printk("%s %d, irqs %d\n", __FUNCTION__,__LINE__, chips->irqs[i]);
 		if (chips->irqs[i] < 0)
 			return chips->irqs[i];
 	}
@@ -229,8 +226,10 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 	chips->gpio_unbanked = gpio_unbanked;
 
 	nbank = DIV_ROUND_UP(ngpio, 32);
-	for (bank = 0; bank < nbank; bank++)
+	for (bank = 0; bank < nbank; bank++) {
 		chips->regs[bank] = gpio_base + offset_array[bank];
+printk("%s %d, nbank %d, bank 0x%x\n", __FUNCTION__,__LINE__, nbank, chips->regs[bank]);
+	}
 
 	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
 	if (ret)
@@ -545,7 +544,7 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
 		g = chips->regs[bank / 2];
 		writel_relaxed(~0, &g->clr_falling);
 		writel_relaxed(~0, &g->clr_rising);
-
+printk("%s, %d, gpio %d, bank %d\n",__FUNCTION__,__LINE__, gpio, bank);
 		/*
 		 * Each chip handles 32 gpios, and each irq bank consists of 16
 		 * gpio irqs. Pass the irq bank's corresponding controller to

      -------------------------

    Regards

       Semon

  • 0 in reply to cesar.xu
    TI__Expert 8551 points
    cesar.xu said:

    These materials cannot solve the current problem. Please confront the current issue directly.

    Regards,

    Hello Cesar

        please try this patch, it use "gpio-reserved-ranges" to reserve GPIOS from used by Linux

        these reserved GPIOs should be used by R5F

        -----------------------------

        

    Fullscreen dts-gpio-chng2.diff Download 
    diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
index bec036b2a..4dff3ca47 100644
--- a/arch/arm64/boot/dts/ti/Makefile
+++ b/arch/arm64/boot/dts/ti/Makefile
@@ -193,6 +193,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-fpdlink-fusion.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-microtips-mf101hie-panel.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-pwm.dtbo
 dtb-$(CONFIG_ARCH_K3) += k3-j722s-evm-v3link-fusion.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-vision-apps.dtbo
+dtb-$(CONFIG_ARCH_K3) += k3-j722s-edgeai-apps.dtbo
 
 # Boards with J784s4 SoC
 dtb-$(CONFIG_ARCH_K3) += k3-am69-sk.dtb
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
index e362bfbb6..cce066bf5 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
+++ b/arch/arm64/boot/dts/ti/k3-j722s-evm.dts
@@ -469,6 +469,10 @@ &cpsw_port1 {
 	status = "okay";
 };
 
+&main_gpio0 {
+	status = "okay";
+};
+
 &main_gpio1 {
 	status = "okay";
 };
diff --git a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
index d3411f80c..6f84a9c77 100644
--- a/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j722s-main.dtsi
@@ -474,6 +474,7 @@ main_pmx0_range: gpio-range {
 &main_gpio0 {
 	gpio-ranges = <&main_pmx0 0 0 32>, <&main_pmx0 32 33 38>,
 			<&main_pmx0 70 72 17>;
+	gpio-reserved-ranges = <16 32>;
 	ti,ngpio = <87>;
 };
 
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 1429e8c02..dbd110260 100644
--- a/drivers/gpio/Makefile
+++ b/drivers/gpio/Makefile
@@ -1,6 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 # generic gpio support: platform drivers, dedicated expander chips, etc
-
+EXTRA_CFLAGS += -DDEBUG
 ccflags-$(CONFIG_DEBUG_GPIO)	+= -DDEBUG
 
 obj-$(CONFIG_GPIOLIB)		+= gpiolib.o
diff --git a/drivers/gpio/gpio-davinci.c b/drivers/gpio/gpio-davinci.c
index f2cc94c26..00dec7e4e 100644
--- a/drivers/gpio/gpio-davinci.c
+++ b/drivers/gpio/gpio-davinci.c
@@ -26,6 +26,8 @@
 #define MAX_REGS_BANKS 5
 #define MAX_INT_PER_BANK 32
 
+#define MAX_RSVRD_GPIO 16
+
 struct davinci_gpio_regs {
 	u32	dir;
 	u32	out_data;
@@ -63,6 +65,8 @@ struct davinci_gpio_controller {
 	struct davinci_gpio_regs context[MAX_REGS_BANKS];
 	u32			binten_context;
 	bool		needs_context_restore;
+	u32                     rsvrd_range[MAX_RSVRD_GPIO];
+	int                     rsvrd_size;
 };
 
 static inline u32 __gpio_mask(unsigned gpio)
@@ -162,7 +166,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 	struct davinci_gpio_controller *chips;
 	struct device *dev = &pdev->dev;
 	struct device_node *dn = dev_of_node(dev);
-
+printk("%s %d, nirq %d\n", __FUNCTION__,__LINE__, nirq);
 	/*
 	 * The gpio banks conceptually expose a segmented bitmap,
 	 * and "ngpio" is one more than the largest zero-based
@@ -188,11 +192,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 		nirq = gpio_unbanked;
 	else
 		nirq = DIV_ROUND_UP(ngpio, 16);
-
-	if (nirq > MAX_INT_PER_BANK) {
-		dev_err(dev, "Too many IRQs!\n");
-		return -EINVAL;
-	}
+printk("%s %d, ngpio %d, nirq %d\n", __FUNCTION__,__LINE__, ngpio, nirq);
 
 	chips = devm_kzalloc(dev, sizeof(*chips), GFP_KERNEL);
 	if (!chips)
@@ -204,6 +204,7 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 
 	for (i = 0; i < nirq; i++) {
 		chips->irqs[i] = platform_get_irq(pdev, i);
+		printk("%s %d, irqs %d\n", __FUNCTION__,__LINE__, chips->irqs[i]);
 		if (chips->irqs[i] < 0)
 			return chips->irqs[i];
 	}
@@ -229,8 +230,10 @@ static int davinci_gpio_probe(struct platform_device *pdev)
 	chips->gpio_unbanked = gpio_unbanked;
 
 	nbank = DIV_ROUND_UP(ngpio, 32);
-	for (bank = 0; bank < nbank; bank++)
+	for (bank = 0; bank < nbank; bank++) {
 		chips->regs[bank] = gpio_base + offset_array[bank];
+printk("%s %d, nbank %d, bank 0x%x\n", __FUNCTION__,__LINE__, nbank, chips->regs[bank]);
+	}
 
 	ret = devm_gpiochip_add_data(dev, &chips->chip, chips);
 	if (ret)
@@ -437,6 +440,42 @@ static struct irq_chip *keystone_gpio_get_irq_chip(unsigned int irq)
 
 static const struct of_device_id davinci_gpio_ids[];
 
+static int davinci_gpio_reserved_ranges(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct davinci_gpio_controller *chips = platform_get_drvdata(pdev);
+	u32 ngpio = chips->chip.ngpio;
+	int size;
+	int ret;
+	u32 ranges[16];
+
+	/* Format is "start, count, ..." */
+	size = chips->rsvrd_size = device_property_count_u32(dev, "gpio-reserved-ranges");
+	if ((chips->rsvrd_size > 0 && chips->rsvrd_size % 2 != 0) || (chips->rsvrd_size < 0)) {
+printk("%s, %d, size %d\n",__FUNCTION__,__LINE__, chips->rsvrd_size);
+		chips->rsvrd_size = 0;
+		return chips->rsvrd_size;
+	}
+	
+	ret = device_property_read_u32_array(dev, "gpio-reserved-ranges",
+					     chips->rsvrd_range, chips->rsvrd_size);
+	if (ret) {
+printk("%s, %d, size %d\n",__FUNCTION__,__LINE__, chips->rsvrd_size);
+		return ret;
+	}
+
+	while (size) {
+		u32 count = chips->rsvrd_range[--size];
+		u32 start = chips->rsvrd_range[--size];
+printk("%s, %d, count %d, start %d\n",__FUNCTION__,__LINE__, count, start);
+		if (start >= ngpio || start + count > ngpio)
+			continue;
+
+	}
+
+	return 0;
+}
+
 /*
  * NOTE:  for suspend/resume, probably best to make a platform_device with
  * suspend_late/resume_resume calls hooking into results of the set_wake()
@@ -532,6 +571,8 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
 
 		goto done;
 	}
+	
+	davinci_gpio_reserved_ranges(pdev);
 
 	/*
 	 * Or, AINTC can handle IRQs for banks of 16 GPIO IRQs, which we
@@ -542,10 +583,26 @@ static int davinci_gpio_irq_setup(struct platform_device *pdev)
 		 * There are register sets for 32 GPIOs. 2 banks of 16
 		 * GPIOs are covered by each set of registers hence divide by 2
 		 */
+		if (chips->rsvrd_size) {
+			int idx = 0;
+			int start;
+			int skip = 0;
+			
+			for (idx = 0; idx < chips->rsvrd_size; idx += 2) {
+				printk("%s, %d, gpio %d, range %d, up %d\n",__FUNCTION__,__LINE__, gpio, chips->rsvrd_range[idx], (chips->rsvrd_range[idx] + 16));
+				if (gpio >= chips->rsvrd_range[idx] && gpio < (chips->rsvrd_range[idx] + chips->rsvrd_range[idx+1])) {
+					skip = 1;
+				}
+			}
+printk("%s, %d, skip %d\n",__FUNCTION__,__LINE__, skip);
+			if (skip) {
+				continue;
+			}
+		}
 		g = chips->regs[bank / 2];
 		writel_relaxed(~0, &g->clr_falling);
 		writel_relaxed(~0, &g->clr_rising);
-
+printk("%s, %d, gpio %d, bank %d\n",__FUNCTION__,__LINE__, gpio, bank);
 		/*
 		 * Each chip handles 32 gpios, and each irq bank consists of 16
 		 * gpio irqs. Pass the irq bank's corresponding controller to

    Regards

       semon