AM62A7-Q1: Question about AM62A SBL startup

Hi,

For your first 3 question I assume by A/B booting you mean selecting which application to boot from 2 application flashed at different address in eMMC and not selecting from boot0 and boot1 partition of eMMC. If this is your use case, then yes, it is possible to achieve this, and you can add the selection logic in both Stage-1 and Stage-2 to boot different application, please refer to this thread: (+) TMDS64EVM: SBL to switch and launch user applications - Processors forum - Processors - TI E2E support forums 

This can give you an idea on how you can implement your usecase, here you would need to add additional bootloader instances for each core you are booting, so in stage-1 you can add an additional bootloader instance for MCU R5, and in stage-2 you can add additional instances for DM R5, A53 and HSM. You can then add your logic to select which image to boot in your SBL stage-1 and stage-2 code. 

Wood Sandal said:

Q4. Is the initialization of DDR carried out in sbl_emmc_linux_stage1? How to configure DDR configuration generated by Sysconfig in code?

Yes, the DDR initialization is done by SBL Stage-1, you can use the DDR Configurator tool for this: SysConfig After configuring this, you can add the generated board_ddrReginit.h file in syscfg file of sbl_emmc_linux_stage1 instead of the default one:

Wood Sandal said:

Q5. In what way can sbl_emmc_linux_stage1 transmit information to sbl_emmc_linux_stage2 or subsequent Linux applications? For example, certain registers or DDR reserved address segments .The purpose of doing so is to use OTA strategy, so that subsequent firmware, such as sbl_emmc_linux_stage2/uboot/Linux APP, can directly perceive the A/B partition selected by sbl_emmc_linux_stage1.

You can use unused sections of DDR to pass information from one stage to another after the DDR initialization is done in Stage-1. 

Wood Sandal said:

Q6. Due to our configuration of MCU R5F and Linux heartbeat, MCU R5F can sense the survival status of Linux. May I ask how to achieve only A53 reset if the Linux kernel freezes during the startup phase?

I assume you would want to trigger a reset of A53 from MCU R5 in this case, please confirm this. I will check and let you know how and if this is possible to achieve.

Best Regards,

Meet.

Hi,Meet Thakar

Thank you for your reply.

Recently I have writed the stage1 code to verify it, the current progress is as follows.
1. The A/B flag has been placed in the EMMC USER partition, and currently stage1 can recognize A/B flag and change it.

2. stage1 can load the corresponding MCU A/B firmware now.

3. Stage1 can pass the corresponding A/B flag through MSRAM at address 0x43C40000. For example, uboot or Linux can also recognize the current A/B flag through MSRAM at address 0x43C40000.

But I have a few questions:
1. The MSRAM area I am using has a starting address of 0x43C40000 and a length of 64KB. Is this specific usage plan defined by myself? Because I found that some of the content here is not set to 0 by default, I am worried that other cores may be using it.

2. Because the objects I upgraded are the cores of MCU R5F firmware and A53 kernel/rootfs, I need to monitor their startup to ensure that my upgrade results are normal.There are many possibilities of failure after upgrading, such as MCU R5F booting fail, A53 kernel panic, or even both failing to start properly. Therefore, Stage1 needs to monitor it to ensure that A/B switching is performed at the bootting fail time.
So how to perform monitoring other core after stage1 start MCU R5F and A53 cores? For example, if ATF, Uboot, or even the kernel panic during startup, I need to restart the entire SOC.

Hi,

Wood Sandal said:

1. The MSRAM area I am using has a starting address of 0x43C40000 and a length of 64KB. Is this specific usage plan defined by myself? Because I found that some of the content here is not set to 0 by default, I am worried that other cores may be using it.

Yes you can use this address as long as any other application is not using this memory.

Wood Sandal said:

So how to perform monitoring other core after stage1 start MCU R5F and A53 cores?

You can use IPC to monitor MCU and A53 cores once their application is booted.

Best Regards,

Meet.

Hi,

Meet Thakar said:

Yes you can use this address as long as any other application is not using this memory.

OK

Meet Thakar said:

You can use IPC to monitor MCU and A53 cores once their application is booted.

IPC shouldn't be on stage1 or 2, right? I understand that stage1 and stage2 will no longer exist after running, so this IPC monitoring needs to be placed in the firmware of DM R5F, right? Do you have any relevant examples?

Best Regards,

Wood.

Wood Sandal said:

IPC shouldn't be on stage1 or 2, right? I understand that stage1 and stage2 will no longer exist after running, so this IPC monitoring needs to be placed in the firmware of DM R5F, right?

This is correct, you won't be able to use IPC in Stage-1 or Stage-2, please refer to this response:  RE: AM62A3-Q1: Monitoring Core status from SBL stage2  

You have to add the IPC in your DM R5 application, you can refer to IPC example available in the MCU+SDK and try to integrate to your DM R5F application. You can also monitor a particular address to monitor whether a core is running or note, you can also refer to this:  RE: AM62A3-Q1: MCU R5 Running after SBL stag1 

Best Regards,

Meet.

Hi,

This page prompts me to access denied.

Hi

I think also that the DM application should be used for this detection.So there are two ways to do this monitoring:
1) DM application is used to monitor a certain memory address, such as the MSRAM I mentioned earlier, and MCU R5F periodically writes with an incremented value to this address. If DM application detects no change, it is considered that MCU R5F is dead.

2) After the MCU R5Fcompletes startup (DM R5F application also completes startup normally), it sends a message to DM application through IPC. If DM R5F does not receive the messages, it is also considered that MCU R5F is dead.

Also, are there any examples of DM R5F reset? Is its reset resetting the entire SOC?

Best Regards,

Wood.

Hi,

OK,I got it.Sincerely thank you for your response recently.

Best Regards,

Wood.