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HI Gokul,
The below patch will help in enabling WKUP UART for the boot logs in SPL Boot flow:
NOTE: When using UART BOOT MODE, ensure that you are loading tiboot3.bin through MCU UART and tispl.bin and u-boot.img through WKUP UART.
J721S2:
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/enable_5F00_wkupuart_5F00_j721s2.patch
J784S4:
https://e2e.ti.com/cfs-file/__key/communityserver-discussions-components-files/791/wkup_5F00_uart_5F00_enable_5F00_j784s4.patch
J7200:
diff --git a/arch/arm/mach-k3/r5/j7200/clk-data.c b/arch/arm/mach-k3/r5/j7200/clk-data.c
index eb8436de..b95d4435 100644
--- a/arch/arm/mach-k3/r5/j7200/clk-data.c
+++ b/arch/arm/mach-k3/r5/j7200/clk-data.c
@@ -62,6 +62,17 @@ static const char * const wkup_i2c0_mcupll_bypass_clksel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
};
+static const char * const wkupusart_clk_sel_out0_parents[] = {
+ "hsdiv4_16fft_mcu_1_hsdivout3_clk",
+ "postdiv2_16fft_main_1_hsdivout5_clk",
+};
+
+static const char * const wkup_usart_mcupll_bypass_clksel_out0_parents[] = {
+ "wkupusart_clk_sel_out0",
+ "gluelogic_hfosc0_clkout",
+};
+
+
static const char * const main_pll_hfosc_sel_out0_parents[] = {
"gluelogic_hfosc0_clkout",
"board_0_hfosc1_clk_out",
@@ -419,6 +430,8 @@ static const struct clk_data clk_list[] = {
CLK_DIV("osbclk0_div_out0", "obsclk0_mux_out0", 0x108000, 8, 8, 0, 0),
CLK_DIV("k3_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
CLK_DIV("k3_pll_ctrl_wrap_wkup_0_chip_div24_clk_clk", "k3_pll_ctrl_wrap_wkup_0_sysclkout_clk", 0x4201011c, 0, 5, 0, 0),
+CLK_MUX("wkupusart_clk_sel_out0", wkupusart_clk_sel_out0_parents, 2, 0x43008064, 0, 1, 0),
+ CLK_MUX("wkup_usart_mcupll_bypass_clksel_out0", wkup_usart_mcupll_bypass_clksel_out0_parents, 2, 0x43008060, 0, 1, 0),
};
static const struct dev_clk soc_dev_clk_data[] = {
@@ -554,6 +567,10 @@ static const struct dev_clk soc_dev_clk_data[] = {
DEV_CLK(323, 0, "main_pll8_sel_extwave_out0"),
DEV_CLK(323, 1, "pllfracf_ssmod_16fft_main_8_foutvcop_clk"),
DEV_CLK(323, 2, "hsdiv0_16fft_main_8_hsdivout0_clk"),
+ DEV_CLK(287, 2, "wkup_usart_mcupll_bypass_clksel_out0"),
+ DEV_CLK(287, 3, "wkupusart_clk_sel_out0"),
+ DEV_CLK(287, 4, "gluelogic_hfosc0_clkout"),
+ DEV_CLK(287, 5, "k3_pll_ctrl_wrap_wkup_0_chip_div1_clk_clk"),
};
const struct ti_k3_clk_platdata j7200_clk_platdata = {
diff --git a/arch/arm/mach-k3/r5/j7200/dev-data.c b/arch/arm/mach-k3/r5/j7200/dev-data.c
index 8ce6796f..ae24e573 100644
--- a/arch/arm/mach-k3/r5/j7200/dev-data.c
+++ b/arch/arm/mach-k3/r5/j7200/dev-data.c
@@ -69,6 +69,7 @@ static struct ti_dev soc_dev_list[] = {
PSC_DEV(103, &soc_lpsc_list[14]),
PSC_DEV(104, &soc_lpsc_list[15]),
PSC_DEV(102, &soc_lpsc_list[16]),
+ PSC_DEV(287, &soc_lpsc_list[13]),
};
const struct ti_k3_pd_platdata j7200_pd_platdata = {
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
index 735ffd3f..2823ff13 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
+++ b/dts/upstream/src/arm64/ti/k3-j7200-common-proc-board.dts
@@ -18,9 +18,9 @@
model = "Texas Instruments J7200 EVM";
aliases {
- serial0 = &wkup_uart0;
+ serial0 = &main_uart0;
serial1 = &mcu_uart0;
- serial2 = &main_uart0;
+ serial2 = &wkup_uart0;
serial3 = &main_uart1;
serial5 = &main_uart3;
mmc0 = &main_sdhci0;
@@ -270,7 +270,7 @@
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
- status = "reserved";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
bootph-all;
diff --git a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
index d9a40b48..c24b1c8f 100644
--- a/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/dts/upstream/src/arm64/ti/k3-j7200-mcu-wakeup.dtsi
@@ -274,11 +274,10 @@
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
+ clock-frequency = <96000000>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 2>;
clock-names = "fclk";
- status = "disabled";
};
mcu_uart0: serial@40a00000 {
diff --git a/board/ti/j721e/j721e.env b/board/ti/j721e/j721e.env
index 54cffa52..37214c3c 100644
--- a/board/ti/j721e/j721e.env
+++ b/board/ti/j721e/j721e.env
@@ -14,7 +14,7 @@ defined(CONFIG_TARGET_J721E_R5_EVM)
name_kern=Image
console=ttyS2,115200n8
-args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x02800000
+args_all=setenv optargs ${optargs} earlycon=ns16550a,mmio32,0x42300000
${mtdparts}
run_kern=booti ${loadaddr} ${rd_spec} ${fdtaddr}
===========
ATF changes
===========
diff --git a/plat/ti/k3/include/platform_def.h b/plat/ti/k3/include/platform_def.h
index 6a05392ad..8a463ba05 100644
--- a/plat/ti/k3/include/platform_def.h
+++ b/plat/ti/k3/include/platform_def.h
@@ -90,14 +90,14 @@
/* Platform default console definitions */
#ifndef K3_USART_BASE
-#define K3_USART_BASE (0x02800000 + 0x10000 * K3_USART)
+#define K3_USART_BASE 0x42300000
#endif
/* USART has a default size for address space */
#define K3_USART_SIZE 0x1000
#ifndef K3_USART_CLK_SPEED
-#define K3_USART_CLK_SPEED 48000000
+#define K3_USART_CLK_SPEED 96000000
#endif
/* Crash console defaults */
===============
OPTEE Changes
===============
diff --git a/core/arch/arm/plat-k3/platform_config.h b/core/arch/arm/plat-k3/platform_config.h
index cffca0a07..d15f9a08f 100644
--- a/core/arch/arm/plat-k3/platform_config.h
+++ b/core/arch/arm/plat-k3/platform_config.h
@@ -9,11 +9,11 @@
#include <mm/generic_ram_layout.h>
-#define UART0_BASE 0x02800000
+#define UART0_BASE 0x42300000
-#define CONSOLE_UART_BASE (UART0_BASE + CFG_CONSOLE_UART * 0x10000)
+#define CONSOLE_UART_BASE UART0_BASE
#define CONSOLE_BAUDRATE 115200
-#define CONSOLE_UART_CLK_IN_HZ 48000000
+#define CONSOLE_UART_CLK_IN_HZ 96000000
#define DRAM0_BASE 0x80000000
#define DRAM0_SIZE 0x80000000
diff --git a/mk/clang.mk b/mk/clang.mk
index d08b26e6f..8a01cd9db 100644
--- a/mk/clang.mk
+++ b/mk/clang.mk
@@ -31,7 +31,7 @@ comp-cflags-warns-clang := -Wno-language-extension-token \
# Note, use the compiler runtime library (libclang_rt.builtins.*.a) instead of
# libgcc for clang
-libgcc$(sm) := $(shell $(CC$(sm)) $(CFLAGS$(arch-bits-$(sm))) \
+libgcc$(sm) := $(shell $(CC$(sm)) $(LIBGCC_LOCATE_CFLAGS) $(CFLAGS$(arch-bits-$(sm))) \
-rtlib=compiler-rt -print-libgcc-file-name 2> /dev/null)
# Core ASLR relies on the executable being ready to run from its preferred load
==================
Kernel Changes
=================
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
index 735ffd3f3..2823ff137 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts
@@ -18,9 +18,9 @@ / {
model = "Texas Instruments J7200 EVM";
aliases {
- serial0 = &wkup_uart0;
+ serial0 = &main_uart0;
serial1 = &mcu_uart0;
- serial2 = &main_uart0;
+ serial2 = &wkup_uart0;
serial3 = &main_uart1;
serial5 = &main_uart3;
mmc0 = &main_sdhci0;
@@ -270,7 +270,7 @@ J721E_IOPAD(0x04, PIN_OUTPUT, 0) /* (T4) USB0_DRVVBUS */
&wkup_uart0 {
/* Wakeup UART is used by System firmware */
- status = "reserved";
+ status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&wkup_uart0_pins_default>;
bootph-all;
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
index d9a40b480..c24b1c8f2 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi
@@ -274,11 +274,10 @@ wkup_uart0: serial@42300000 {
compatible = "ti,j721e-uart", "ti,am654-uart";
reg = <0x00 0x42300000 0x00 0x100>;
interrupts = <GIC_SPI 897 IRQ_TYPE_LEVEL_HIGH>;
- clock-frequency = <48000000>;
+ clock-frequency = <96000000>;
power-domains = <&k3_pds 287 TI_SCI_PD_EXCLUSIVE>;
clocks = <&k3_clks 287 2>;
clock-names = "fclk";
- status = "disabled";
};
mcu_uart0: serial@40a00000 {
Build Steps:
============
Building UBOOT:
Building ATF:
Building OPTEE:
Regards
Gokul