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Original question:

PROCESSOR-SDK-J722S: J722s: is it possible to alloc more gpio interrupt for mcu20?

PROCESSOR-SDK-J722S: J722s is it possible to extend mcu20 GPIO interrupt by using dma interrupt ?

?? ?
Intellectual 270 points
Part Number: PROCESSOR-SDK-J722S

Tool/software: 

Hi TI expert,
    1. i am using J722s evm  and sdk v11  example code as environment. sdcard, spl boot mode.
      2. my target is to use 12 GPIO single pin interrupt on mcu20.
      3. since mcu20 only and 8(actual is 6) interrupt entry(16-21), and then i found interrupt start from 66(DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_154), could gpio pin interrupt router to here?
         so, the whole chain maybe like this:
       GPIO0_xxx  -> | Main GPIOMUX INTROUTER0| -> DMASSO_INTAGGR_0/24-31  ( how to router?? ) ->  MCU20 INTR_IN_66 (DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_154) 

    4. is there any doc to describe   DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_xxx and DMASSO_INTAGGR_0 xxx, i want to know what is "VINTR_PEND" and how to use it.

     thanks
  • 0
    TI__Mastermind 19370 points

    Hi,

    ?? ? said:
    2. my target is to use 12 GPIO single pin interrupt on mcu20.
    3. since mcu20 only and 8(actual is 6) interrupt entry(16-21)

    Although there are only 8 interrupts available on MCU2_0 for GPIO, are you able to use banked interrupts? This way you could route all 12 GPIO interrupts to MCU2_0 with no issues.

    Are you using any of the GPIO banked interrupts on other cores? If so, which ones?

    ?? ? said:
    3. since mcu20 only and 8(actual is 6) interrupt entry(16-21), and then i found interrupt start from 66(DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_154), could gpio pin interrupt router to here?
    so, the whole chain maybe like this:
    GPIO0_xxx -> | Main GPIOMUX INTROUTER0| -> DMASSO_INTAGGR_0/24-31 ( how to router?? ) -> MCU20 INTR_IN_66 (DMASS0_INTAGGR_0_INTAGGR_VINTR_PEND_154)

    You should be able to route GPIO interrupts though DMASS as there is an interrupt path. However, we do not have any examples of this nor has it been tested or validated by TI.

    GPIO -> MAIN_GPIOMUX_INTROUTER -> DMASS_INTRAGGR_0 [16-25] -> R5FSS0_CORE0_INTR [64-79]

    Thanks,

    Neehar