MLC NAND flash Interface to GPMC (OMAP 3530)

babu reddy

Intellectual 580 points

hi,

am working OMAP 3530, i have to interface 4 GByte nand flash to CS0 (chip select 0) of GPMC,

which is MLC NAND flash from Micron, Part number is MT29F32G08CBACAWP.

my question is whether the OMAP 3530 will support MLC NAND flashes or SLC NAND flashes?

what are the basic settings to do, am using Angstrom linux, Devkit8000 board,

and also suggest me if any settings are required in x-loader, u-boot or uImage ?

thanks and Regards

N Reddy

over 13 years ago

0 Michael T over 13 years ago

TI__Expert 6735 points

Please look at the following thread which discusses MLC NAND flash:

https://e2e.ti.com/support/dsp/omap_applications_processors/int_omap35x_dsps/f/45/t/1494.aspx

Regards,

Michael T

0 babu reddy over 13 years ago in reply to Michael T

Intellectual 580 points

hi Micheal,

the link you have suggested is not working, am getting an message like below..

Group Not Found

The requested Group cannot be found

please suggest me...

thanks and regards

N Reddy

0 Jeff Culverhouse over 13 years ago in reply to babu reddy

TI__Genius 9190 points

Hello Babu,

Sorry, that link was to an internal TI site. It was just basically stating that MLC NANDs are not supported on the OMAP35x devices and it is best to move to a managed NAND like eMMC if you need very large density NAND devices.

0 babu reddy over 13 years ago in reply to Jeff Culverhouse

Intellectual 580 points

hi Jeff Culverhous

thanks for your response,

i am using OMAP3530DZCBB package,

i have few questions

1)then is it possible to use SLC NAND flash of size 4 Gbyte?

2) is it possible to interface 4 GBytes of single NAND flash to GMPC?

3) in chapter 2.2 global memory mapping (page number 180 of OMAP 3530 TRM)

SDRC

CS0 – 0x8000 0000 0x9FFF FFFF 512MB SDRC / SMS SDRAM (5)
CS1 – 0xA000 0000 0xBFFF FFFF 512MB SDRC / SMS SDRAM (5)
so each chip select can support 512 MB SDRAM..

in chapter 1.3.4 External Memory Interfaces (page number 159 of OMAP 3530 TRM),

- "16-bit or 32-bit data, 2 chip-selects, configurations for a maximum of 1 G-byte address space per chip-select "

what is the meaning of above statement?

what is the maximum size of SDRAM i can interface to each chip select in SDRC?

thanks and regards

N Reddy

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MLC NAND flash Interface to GPMC (OMAP 3530)