AM62A7-Q1: Boot Issue with AM62A7-Q1

Please use the DDR Register Configuration tool: https://dev.ti.com/sysconfig/?product=Processor_DDR_Config&device=AM62Ax to configure DDR for your specific system.  Instructions are in the README link in the tool.  Since the devices are the same, just different temp grade, you probably just have to tweak some of the IO settings (drive strength or termination).  Did you perform board simulations to arrive at optimal settings for best signal integrity?

Once you have done this, please add the patch described here: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1358039/faq-board-bring-up-tips-for-sitara-devices-am64x-am243x-am62x-am62l-am62ax-am62d-q1-am62px#:~:text=Getting%20DDR%20register%20dump%20after%20initialization%C2%A0

and post the register dump to help further debug.

Regards,

James

Thanks for the suggestion .

We have configured the LPDDR from the shared link and update the header files in each case mention below, We received the same status. We are updating the files on mcu_plus_sdk_am62ax_10_01_00_33. Previously we have tried in Linux and now trying to boot from UART.
please review and provide the addition details on over it.

Test cases in header file: 

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 80ohm

Not working
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FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 40ohm
Termination: DQ ODT (FSP2) - 60Ohm

not working
---------------------------------------------------
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 60ohm
Termination: DQ ODT (FSP2) - 60Ohm

not working
---------------------------------------------------
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 60ohm
Termination: DQ ODT (FSP2) - 60Ohm
RL: Read Latency / nRTP - FSP2 - 24

---------------------------------------------------
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 60ohm
Termination: DQ ODT (FSP2) - 60Ohm
ODT Pull-Down DQ/DM - 60Ohm

not working
---------------------------------------------------
--------------------------------------------------

FSP2 Frequency (MHz) 800Mhz
DDR Density (per channel) (Gb) 16
Operating Temperature Range -40c to 105C

Termination: CA ODT (FSP2) - 60ohm
Termination: DQ ODT (FSP2) - 60Ohm
ODT Pull-Down DQ/DM - 60Ohm
Driver Pull-Up CSn - 48ohm

Please try the patch i mentioned earlier.  Can you send your schematic?

Regards,

James

During boot, the RESET_N signal on LPDDR4 goes high after the SPL Stage 1 on our custom board. However, it consistently remains low in TI EVM.
According to the LPDDR4 datasheet, RESET_N should transition high during initialization.

The reset signal does go high on the EVM when the bootloader loads correctly.  It may not be going high because boot is failing.

Regards,

James

The SoC bootloader loads correctly. Our concern is with the DDR0_RESET_N signal of the LPDDR4, which goes high on our custom board.
However, according to the DDR datasheet, the timing diagram it also indicates a RESET_N high during  initilization. but during spl stage 2 error message recieve:

 U-Boot SPL 2023.04-ti-gf9b966c67473 (Mar 19 2024 - 20:31:40 +0000)
SYSFW ABI: 3.1 (firmware rev 0x0009 '9.2.7--v09.02.07 (Kool Koala)')
am62a_init: board_init_f done
SPL initial stack usage: 17064 bytes

Please check whether the reset signal (RESET_N) is high during initialization.
Also, how can we obtain detailed logs for this process?

This seems to be the same question: https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1549818/am62a7-error-at-the-time-flashing-sbl_uart_uniflash_stage2-release-appimage-hs_fs----incorrect-magic-number-in-response-header

Please try the steps from this thread.  Also send schematic and implement the patch as mentioned.  The RESET signal will conform to the timing diagram when the board is properly booting.

Regards,

James