C6474 can't write data to DDR2

The DDR2 module on my TMS320C6474 board can't work well.Data can't be written to any DDR2 

address.The DDR2 chip we used is MT47H64M16-3E. When I write a data to a DDR2 address(from 

this address 0x80000000) a large number of addresses turn red (changed).We used the 

EVM_C6474 project 

Ddr2_narrow_mode_read_write_example.pjt .Because of the DDRCLKOUTP signal on low 16-bit 

address chip of DDR2(32bit) is abnormal, I have to test only the high 16-bit address chip of 

DDR2. We use 50Mhz DDR2 clock.So the project should be modified as follows:


#include <csl_ddr2.h>
#include <stdio.h>

/** Result - Passed */
#define PASSED 	    1
/** Result - Failed */
#define FAILED 	    0

/** Data count(number write/readbacks) */
#define DATA_CNT    10

#define EMIFB_CE0_BASE_ADDR            (0x80000000u)
#define SDRAM_REFRESH_RATE             (0x79E)

/* Handle for the DDR2 instance */
CSL_Ddr2Handle    hDdr2;

void ddr2ReadWrite(void);


void main (
    void
)
{   
    /* read_write functionality of DDR2 */
    ddr2ReadWrite();   
    return; 
}


void ddr2ReadWrite (
    void
)
{
    volatile Uint32     result, index ;
    Uint16              tempData; 
    CSL_Ddr2Obj         ddr2Obj;
    CSL_Status          status;
    CSL_Ddr2HwSetup     hwSetup ;     
    
    //CSL_Ddr2Timing1     tim1 = CSL_DDR2_TIMING1_DEFAULTS;
    //CSL_Ddr2Timing2     tim2 = CSL_DDR2_TIMING2_DEFAULTS;
    CSL_Ddr2Timing1     tim1 = CSL_DDR2_TIMING1_250;
    CSL_Ddr2Timing2     tim2 = CSL_DDR2_TIMING2_250;
    CSL_Ddr2Settings    set  = CSL_DDR2_SETTING_DEFAULTS;    

    /* Pointer that points to SDRAM start area */
    Uint16 *pDdr2Data = (Uint16 *)EMIFB_CE0_BASE_ADDR ;

    /* Clear local data structures */   
    memset(&ddr2Obj, 0, sizeof(CSL_Ddr2Obj));      
    memset(&hwSetup, 0, sizeof(CSL_Ddr2HwSetup));
    
    /* setup the hardware parameters */
    hwSetup.refreshRate = SDRAM_REFRESH_RATE;
    hwSetup.readLatncy = CSL_DDR2_DMCCTL_RL_RESETVAL;	
    //hwSetup.readLatncy = CSL_DDR2_DMCCTL_RESETVAL;
    hwSetup.timing1Param = &tim1;
    hwSetup.timing2Param = &tim2;
    set.narrowMode = CSL_DDR2_NARROW_MODE;
    set.ddr2En = 0x1;
    set.ddrEn = 0x1;
    set.sdramEn = 0x1;
    
    set.casLatncy = CSL_DDR2_CAS_LATENCY_4;
    set.ibank = CSL_DDR2_8_SDRAM_BANKS;
    set.pageSize = CSL_DDR2_1024WORD_10COL_ADDR;     

    hwSetup.setParam = &set;    
        
    /* Initialize DDR2 CSL module */
    status = CSL_ddr2Init(NULL);
    if (status != CSL_SOK) {
        printf ("DDR2 EMIF: Initialization... Failed.\n");
        printf ("\tReason: CSL_ddr2Init failed. [status = 0x%x].\n", status);		
        return;
    }
    else {
        printf ("DDR2 EMIF: Module Initialization... Passed.\n");
    }

    /* Opening the DDR2 instance */
    hDdr2 =  CSL_ddr2Open (&ddr2Obj, CSL_DDR2, NULL, &status);
    if ((status != CSL_SOK) || (hDdr2 == NULL)) {
        printf ("DDR2 EMIF: Opening instance... Failed.\n");
        printf ("\tReason: Error opening the instance. [status = 0x%x, hDdr2 = \
                   0x%x]\n", status, hDdr2);		
        return;
    }
    else {
        printf ("DDR2 EMIF: Module instance open... Passed.\n");
    }

    /* Setting up configuration parameter using HwSetup */
    status =  CSL_ddr2HwSetup (hDdr2, &hwSetup);                     
    if (status != CSL_SOK) {
        printf ("DDR2 EMIF: Hardware setup... Failed.\n");
        printf ("\tReason: Unknown error in HW Setup.\n");        
    }
    else {
        printf ("DDR2 EMIF: Module Hardware setup... Passed.\n");
    }
    
    /* Clearing old values with a recognizable value into DDR2 SDRAM area. 
     * This is to ensure that data from previous run, doesn't fool us to 
     * pass the test 
     */
    //write high 16bit address
    tempData = 0xdead;
    for (index  = 1; index <= DATA_CNT; index+=2) {
	    pDdr2Data[index] =  tempData;
    }

	/* Write **valid** values into SDRAM area. */
     tempData = 0x5678;
	for (index = 1; index <= DATA_CNT; index+=2) {
		pDdr2Data[index] = tempData;
	}

	/* Verify that the data was indeed written */
	result = PASSED;
	for (index = 1; index <= DATA_CNT; index+=2) {
		if (pDdr2Data[index] != tempData) {
			result = FAILED;			          
			break ;
		}
	}

	/* Print the appropriate message based on result */
	if (result == PASSED) {		
	   	printf("\nWrite to and Read from DDR2 SDRAM .....passed\n"); 
	}
    else {     	
	   	printf("\nWrite to and Read from DDR2 SDRAM ......failed\n"); 
        printf("\tError in data read.[status = 0x%x]\n", status);
    }   
}



SDTIM1, SDTIM2 and other  REG definitions were set as the TMS320C6474DSP DDR2 Memory 

Controller User's Guide specified.

The Stdout displayed :
DDR2 EMIF: Module Initialization... Passed.
DDR2 EMIF: Module instance open... Passed.
DDR2 EMIF: Module Hardware setup... Passed.

Write to and Read from DDR2 SDRAM ......failed
Error in data read.[status = 0x1]

By the way,I had use this project on EVM_C6474 board(66Mhz DDR2 clock).The project can pass on it .
Please help me checking out where the problem is.