AM67: Ethernet RX is not capturing packets

Hi,

Are you able to see any packets being received on the phy using phy statistics?

From the logs it seems that the link was successfully set up at 100M RMII Full duplex. But the CPSW IP is not receiving any packets otherwise we expect to see frames incremented in "rx_good_frames". Even if there is some issue with the frame, there should be some err/drop statistic incrementing. That is also not the case.

I thing the traffic is not even reaching the SoC. can you probe the RMII Rx lines and see if you see any activity there? Please also check the clocks in that case.

Can you also check the clock dump using the command "k3conf dump clocks 13" for checking the internal clocks.

Regards,
Tanmay

Hi Tanmay,

Looks like perhaps the clock setting is the issue. I can see the clocks on the wires with the scope, but RMII isn't set, and RGMII is set, it's leftover from the devkit dts. How can I update the device tree to set the RMII instead of RGMII clock?

k3conf dump clocks 13
|------------------------------------------------------------------------------|
| VERSION INFO |
|------------------------------------------------------------------------------|
| K3CONF | (version 0.3-nogit built Thu Jul 25 14:13:02 UTC 2024) |
| SoC | J722S SR1.0 |
| SYSFW | ABI: 4.0 (firmware version 0x000a '10.1.6--v10.01.06 (Fiery Fox))') |
|------------------------------------------------------------------------------|

|---------------------------------------------------------------------------------------------------------------------------------------|
| Device ID | Clock ID | Clock Name | Status | Clock Frequency |
|---------------------------------------------------------------------------------------------------------------------------------------|
| 13 | 0 | DEV_CPSW0_CPPI_CLK_CLK | CLK_STATE_READY | 250000000 |
| 13 | 1 | DEV_CPSW0_CPTS_GENF0 | CLK_STATE_READY | 0 |
| 13 | 2 | DEV_CPSW0_CPTS_GENF1 | CLK_STATE_READY | 0 |
| 13 | 3 | DEV_CPSW0_CPTS_RFT_CLK | CLK_STATE_READY | 500000000 |
| 13 | 4 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_2_HSDIVOUT5_CLK | CLK_STATE_READY | 500000000 |
| 13 | 5 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_POSTDIV4_16FF_MAIN_0_HSDIVOUT6_CLK | CLK_STATE_READY | 200000000 |
| 13 | 6 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_CP_GEMAC_CPTS0_RFT_CLK_OUT | CLK_STATE_READY | 0 |
| 13 | 8 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_MCU_EXT_REFCLK0_OUT | CLK_STATE_READY | 0 |
| 13 | 9 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_BOARD_0_EXT_REFCLK1_OUT | CLK_STATE_READY | 0 |
| 13 | 10 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_WIZ16B2M4CT_MAIN_1_IP1_LN0_TXMCLK | CLK_STATE_READY | 0 |
| 13 | 11 | DEV_CPSW0_CPTS_RFT_CLK_PARENT_SAM62_PLL_CTRL_WRAP_MAIN_0_CHIP_DIV1_CLK_CLK | CLK_STATE_READY | 500000000 |
| 13 | 13 | DEV_CPSW0_GMII1_MR_CLK | CLK_STATE_READY | 25000000 |
| 13 | 14 | DEV_CPSW0_GMII1_MT_CLK | CLK_STATE_READY | 25000000 |
| 13 | 15 | DEV_CPSW0_GMII2_MR_CLK | CLK_STATE_READY | 25000000 |
| 13 | 16 | DEV_CPSW0_GMII2_MT_CLK | CLK_STATE_READY | 25000000 |
| 13 | 17 | DEV_CPSW0_GMII_RFT_CLK | CLK_STATE_READY | 125000000 |
| 13 | 18 | DEV_CPSW0_MDIO_MDCLK_O | CLK_STATE_READY | 0 |
| 13 | 19 | DEV_CPSW0_RGMII_MHZ_250_CLK | CLK_STATE_READY | 250000000 |
| 13 | 20 | DEV_CPSW0_RGMII_MHZ_50_CLK | CLK_STATE_READY | 50000000 |
| 13 | 21 | DEV_CPSW0_RGMII_MHZ_5_CLK | CLK_STATE_READY | 5000000 |
| 13 | 22 | DEV_CPSW0_RMII1_MHZ_50_CLK | CLK_STATE_READY | 0 |
| 13 | 23 | DEV_CPSW0_RMII2_MHZ_50_CLK | CLK_STATE_READY | 0 |
| 13 | 24 | DEV_CPSW0_SERDES1_REFCLK | CLK_STATE_READY | 0 |
| 13 | 25 | DEV_CPSW0_SERDES1_RXCLK | CLK_STATE_READY | 0 |
| 13 | 26 | DEV_CPSW0_SERDES1_RXFCLK | CLK_STATE_READY | 0 |
| 13 | 27 | DEV_CPSW0_SERDES1_TXCLK | CLK_STATE_READY | 0 |
| 13 | 28 | DEV_CPSW0_SERDES1_TXFCLK | CLK_STATE_READY | 0 |
| 13 | 29 | DEV_CPSW0_SERDES1_TXMCLK | CLK_STATE_READY | 0 |
| 13 | 30 | DEV_CPSW0_SERDES2_REFCLK | CLK_STATE_READY | 0 |
| 13 | 31 | DEV_CPSW0_SERDES2_RXCLK | CLK_STATE_READY | 0 |
| 13 | 32 | DEV_CPSW0_SERDES2_RXFCLK | CLK_STATE_READY | 0 |
| 13 | 33 | DEV_CPSW0_SERDES2_TXCLK | CLK_STATE_READY | 0 |
| 13 | 34 | DEV_CPSW0_SERDES2_TXFCLK | CLK_STATE_READY | 0 |
| 13 | 35 | DEV_CPSW0_SERDES2_TXMCLK | CLK_STATE_READY | 0 |
|---------------------------------------------------------------------------------------------------------------------------------------|

I see in the device tree:
cpsw3g: ethernet@8000000 {
...
clocks = <&k3_clks 13 0>;
assigned-clocks = <&k3_clks 13 3>;
assigned-clock-parents = <&k3_clks 13 11>;

I see traffic on the RMII RXD0/RXD1 pins during the first communication, then it stops.

ping 192.168.10.2

Pinging 192.168.10.2 with 32 bytes of data:
Reply from 192.168.10.1: Destination host unreachable. <- RXD0/RXD1 waveform here
Request timed out. <- No RXD0/RXD1 waveform

If I ping out from the AM67 to the host, I get consistent communication back on the RXD0/RXD1 lines.
TXD0/TXD1 are working normally it seems, and traffic on RXD0/RXD1 are not getting consumed somewhere.

arp -a on the windows host shows the AM67 mac address, but I see no received traffic using tcpdump on AM67.

Hi,

Is the clock for RMII being sources from internal clock or you have connected external clock to the "RMII_REF_CLK" pin?

If its an internal RMII clock being used, can you confirm that you are looping back the clock in schematic.

Can you confirm the value of reg 0x00108010 is 0 in case of internal clk loopback.

Regards,
Tanmay

Hi Tanmay, It's an external clock I think.
We have pin AE27, RMII1_REF_CLK tied to the phy chip, and I see it oscillating at 50MHz.

devmem2 0x00108010
/dev/mem opened.
Memory mapped at address 0xffffbade8000.
Read at address 0x00108010 (0xffffbade8010): 0x00000000

Hi Tanmay, is there any update on this?

Hi,

Sorry for the delay on this. 

Evan Williams said:

Hi Tanmay, It's an external clock I think.
We have pin AE27, RMII1_REF_CLK tied to the phy chip, and I see it oscillating at 50MHz.

If you can see the line oscillating at 50MHz, that's a good sign. It also removes the dependency from the phy-gmii-sel driver to set anything. Its only required in internal clocking mode.

When you receive any frames, do you see any drops being incremented in the output of "ethtool -S <IF_NAME>"?

Can you share the device-tree updates you have done for this CPSW node.

There is per port MAC control and status register at address:

• Control : 0x08000330h + (j*0x100) where j is the port number
• Status :  0x08000334h + (j*0x100) where j is the port number

Can you check what is value of the registers for the RMII port.

Regards,
Tanmay

Hi Tanmay,

I confirmed the 50MHz comes from the chip by removing one of our series 33 ohm resistors.
I found another post saying all series 33 ohms needed removed, so I removed them and it didn't seem to make a difference.

There are no dropped frames.

Control and Status registers are returning all 0's
The excel sheet says +formula for the registers, do you know where I can find the formula value (0x100) for future reference?

Is IFCTL_A supposed to be set to 1?

root@j722s-evm:~# devmem2 0x08000330
/dev/mem opened.
Memory mapped at address 0xffff85968000.
Read at address 0x08000330 (0xffff85968330): 0x00000000
root@j722s-evm:~# devmem2 0x08000334
/dev/mem opened.
Memory mapped at address 0xffff8117e000.
Read at address 0x08000334 (0xffff8117e334): 0x00000000
root@j722s-evm:~# devmem2 0x08000430
/dev/mem opened.
Memory mapped at address 0xffffb3723000.
Read at address 0x08000430 (0xffffb3723430): 0x00000000
root@j722s-evm:~# devmem2 0x08000434
/dev/mem opened.
Memory mapped at address 0xffffad46c000.
Read at address 0x08000434 (0xffffad46c434): 0x00000000
root@j722s-evm:~# devmem2 0x08000530
/dev/mem opened.
Memory mapped at address 0xffff9a4cb000.
Read at address 0x08000530 (0xffff9a4cb530): 0x00000000
root@j722s-evm:~# devmem2 0x08000534
/dev/mem opened.
Memory mapped at address 0xffff954fe000.
Read at address 0x08000534 (0xffff954fe534): 0x00000000

Here are device tree changes.
The micrel changes are mostly copied from an imx dts. The clock_ksz8081_out is unused, I think it's supposed to go somewhere.

&cpsw3g {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&rmii1_pins_default>;
};

&cpsw3g_mdio {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&mdio_pins_default>;

cpsw3g_phy0: ethernet-phy@0 {
reset-gpios = <&main_gpio0 60 GPIO_ACTIVE_LOW>;
reset-assert-us = <10000>;
reset-deassert-us = <300>;
clocks = <&clock_ksz8081_in>;
clock-names = "rmii-ref";
reg = <0>;
};
};

&cpsw_port1 {
phy-mode = "rmii";
phy-handle = <&cpsw3g_phy0>;
};

&{/} {
clock_ksz8081_in: clock-ksz8081-in {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};

clock_ksz8081_out: clock-ksz8081-out {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
clock-output-names = "enet1_ref_pad";
};

};

Hi Tanmay,

Even though the registers don't seem to be showing with devmem2, the values should be set?
I modified the code, and I think it is trying to set them in the function: 
am65_cpsw_nuss_mac_link_up

[ 9.839619] am65-cpsw-nuss 8000000.ethernet eth0: PHY [8000f00.mdio:00] driver [Micrel KSZ8081 or KSZ8091] (irq=POLL)
[ 9.839682] am65-cpsw-nuss 8000000.ethernet eth0: configuring for phy/rmii link mode
[ 14.946640] am65-cpsw-nuss 8000000.ethernet: [2121]: NOT Setting CPSW_SL_CTL_EXT_EN
[ 14.946689] am65-cpsw-nuss 8000000.ethernet: [2125]: Setting CPSW_SL_CTL_IFCTL_A
[ 14.946697] am65-cpsw-nuss 8000000.ethernet: [2136]: Setting CPSW_SL_CTL_TX_FLOW_EN
[ 14.946702] am65-cpsw-nuss 8000000.ethernet: [2144]: Setting CPSW_SL_CTL_RX_FLOW_EN
[ 14.947394] am65-cpsw-nuss 8000000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx

Using the offsets in the code, I found them here:

devmem2 0x8022330
/dev/mem opened.
Memory mapped at address 0xffff8daae000.
Read at address 0x08022330 (0xffff8daae330): 0x00008039

devmem2 0x8022334
/dev/mem opened.
Memory mapped at address 0xffffa0962000.
Read at address 0x08022334 (0xffffa0962334): 0xF0000000