Tool/software:
Hi TI expert,
1. i am using J722s evm and sdk v11 example code as environment. sdcard, spl boot mode.
2. my target is to create ipc communication between cores, including mcu r5f, main mcu, wkup mcu , a53.
3. currently, i am working on main mcu to r5f mcu. based on code mcu-sdk ipc demo and vision app mcu20 code.
4. i think the ipc exchange data should be using share memory, which i think is at 0xa5000000 shared for all cores.
5. in mcu r5f sdk, it create by syscfg-gui, and in main mcu20, it's already in appIpcInit().
my question is:
1. for "vringTxBaseAddr" and "vringRxBaseAddr", it's different setting in mcur5f and mcu20, since the buffer, mcu r5f is system predefine offset , mcu20 is dynamic increased allocated, it not same.
2. for "vringTxBaseAddr" and "vringRxBaseAddr", why syscfg generated code missing a53 core, mcu20 code missing mcu r5f.
here is the log
mcu r5f channel index: total 20 channel
wkup_r5fss0_0 => {"mcu": 4, "wkup":-1, "main": 5, "c75ss0_0": 6, "c75ss1_0": 7}
main_r5fss0_0 => {"mcu": 8, "wkup": 9, "main":-1, "c75ss0_0":10, "c75ss1_0":11}
c75ss0_0 => {"mcu":12, "wkup":13, "main":14, "c75ss0_0":-1, "c75ss1_0":15}
c75ss1_0 => {"mcu":16, "wkup":17, "main":18, "c75ss0_0":19, "c75ss1_0":-1}
[MCU2_0] 2.897980 s: creating 1 rxTxMap 1: 5 -> 3
[MCU2_0] 2.897993 s: creating 1 rxTxMap 2: 5 -> 4
[MCU2_0] 2.898007 s: creating 1 rxTxMap 3: 2 -> 5
[MCU2_0] 2.898020 s: creating 1 rxTxMap 4: 2 -> 3
[MCU2_0] 2.898034 s: creating 1 rxTxMap 5: 2 -> 4
[MCU2_0] 2.898047 s: creating 1 rxTxMap 6: 3 -> 5
[MCU2_0] 2.898060 s: creating 1 rxTxMap 7: 3 -> 2
[MCU2_0] 2.898073 s: creating 1 rxTxMap 8: 3 -> 4
[MCU2_0] 2.898086 s: creating 1 rxTxMap 9: 4 -> 5
[MCU2_0] 2.898100 s: creating 1 rxTxMap 10: 4 -> 2
[MCU2_0] 2.898114 s: creating 1 rxTxMap 11: 4 -> 3
thanks
