Other Parts Discussed in Thread: SYSCONFIG
Tool/software:
Hi TI,
we are getting VissWdtimerErrorCb from ISP module if we read below VPAC registers periodically.
{ "CSL_MSC_CONTROL", CSL_VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP_BASE + CSL_MSC_CONTROL, CSL_MSC_CONTROL_MSC_ENABLE_MASK, CSL_MSC_CONTROL_MSC_ENABLE_SHIFT, CSL_MSC_CONTROL_MSC_ENABLE_MAX },
{ "CSL_MSC_COEF_SP_C210", CSL_VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP_BASE + CSL_MSC_COEF_SP_C210(0), CSL_MSC_COEF_SP_C210_FIR_C2_MASK, CSL_MSC_COEF_SP_C210_FIR_C2_SHIFT, CSL_MSC_COEF_SP_C210_FIR_C2_MAX },
{ "CSL_MSC_COEF_SP_C43", CSL_VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP_BASE + CSL_MSC_COEF_SP_C43(0), CSL_MSC_COEF_SP_C43_FIR_C4_MASK, CSL_MSC_COEF_SP_C43_FIR_C4_SHIFT, CSL_MSC_COEF_SP_C43_FIR_C4_MAX },
{ "CSL_MSC_COEF_MP_PH_C210", CSL_VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP_BASE + CSL_MSC_COEF_MP_PH_C210(0, 0), CSL_MSC_COEF_MP_PH_C210_FIR_C2_MASK, CSL_MSC_COEF_MP_PH_C210_FIR_C2_SHIFT, CSL_MSC_COEF_MP_PH_C210_FIR_C2_MAX },
{ "CSL_MSC_COEF_MP_PH_C43", CSL_VPAC0_PAR_VPAC_MSC_CFG_VP_CFG_VP_BASE + CSL_MSC_COEF_MP_PH_C43(0, 0), CSL_MSC_COEF_MP_PH_C43_FIR_C4_MASK, CSL_MSC_COEF_MP_PH_C43_FIR_C4_SHIFT, CSL_MSC_COEF_MP_PH_C43_FIR_C4_MAX },
{ "CSL_LDC_CORE_DUALOUT_CFG", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_DUALOUT_CFG, CSL_LDC_CORE_DUALOUT_CFG_COUT_BITDPTH_MASK, CSL_LDC_CORE_DUALOUT_CFG_COUT_BITDPTH_SHIFT, CSL_LDC_CORE_DUALOUT_CFG_COUT_BITDPTH_MAX },
{ "CSL_LDC_CORE_IBUF_PIX_START", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_IBUF_PIX_START, CSL_LDC_CORE_IBUF_PIX_START_STARTY_MASK, CSL_LDC_CORE_IBUF_PIX_START_STARTY_SHIFT, CSL_LDC_CORE_IBUF_PIX_START_STARTY_MAX },
{ "CSL_LDC_CORE_HYBD_CBUFF_PARAM", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CBUFF_PARAM, CSL_LDC_CORE_HYBD_CBUFF_PARAM_STARTLINE_MASK, CSL_LDC_CORE_HYBD_CBUFF_PARAM_STARTLINE_SHIFT, CSL_LDC_CORE_HYBD_CBUFF_PARAM_STARTLINE_MAX },
{ "CSL_LDC_CORE_HYBD_CBUFF_BA_H", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CBUFF_BA_H, CSL_LDC_CORE_HYBD_CBUFF_BA_H_ADDR_MASK, CSL_LDC_CORE_HYBD_CBUFF_BA_H_ADDR_SHIFT, CSL_LDC_CORE_HYBD_CBUFF_BA_H_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_CBUFF_BA_L", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CBUFF_BA_L, CSL_LDC_CORE_HYBD_CBUFF_BA_L_ADDR_MASK, CSL_LDC_CORE_HYBD_CBUFF_BA_L_ADDR_SHIFT, CSL_LDC_CORE_HYBD_CBUFF_BA_L_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_BUFF2_BA_H", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_BUFF2_BA_H, CSL_LDC_CORE_HYBD_BUFF2_BA_H_ADDR_MASK, CSL_LDC_CORE_HYBD_BUFF2_BA_H_ADDR_SHIFT, CSL_LDC_CORE_HYBD_BUFF2_BA_H_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_BUFF2_BA_L", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_BUFF2_BA_L, CSL_LDC_CORE_HYBD_BUFF2_BA_L_ADDR_MASK, CSL_LDC_CORE_HYBD_BUFF2_BA_L_ADDR_SHIFT, CSL_LDC_CORE_HYBD_BUFF2_BA_L_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_CHCBUFF_PARAM", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CHCBUFF_PARAM, CSL_LDC_CORE_HYBD_CHCBUFF_PARAM_STARTLINE_MASK, CSL_LDC_CORE_HYBD_CHCBUFF_PARAM_STARTLINE_SHIFT, CSL_LDC_CORE_HYBD_CHCBUFF_PARAM_STARTLINE_MAX },
{ "CSL_LDC_CORE_HYBD_CHCBUFF_BA_H", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CHCBUFF_BA_H, CSL_LDC_CORE_HYBD_CHCBUFF_BA_H_ADDR_MASK, CSL_LDC_CORE_HYBD_CHCBUFF_BA_H_ADDR_SHIFT, CSL_LDC_CORE_HYBD_CHCBUFF_BA_H_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_CHCBUFF_BA_L", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CHCBUFF_BA_L, CSL_LDC_CORE_HYBD_CHCBUFF_BA_L_ADDR_MASK, CSL_LDC_CORE_HYBD_CHCBUFF_BA_L_ADDR_SHIFT, CSL_LDC_CORE_HYBD_CHCBUFF_BA_L_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_CHBUFF2_BA_H", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CHBUFF2_BA_H, CSL_LDC_CORE_HYBD_CHBUFF2_BA_H_ADDR_MASK, CSL_LDC_CORE_HYBD_CHBUFF2_BA_H_ADDR_SHIFT, CSL_LDC_CORE_HYBD_CHBUFF2_BA_H_ADDR_MAX },
{ "CSL_LDC_CORE_HYBD_CHBUFF2_BA_L", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_MMR_VBUSP_BASE + CSL_LDC_CORE_HYBD_CHBUFF2_BA_L, CSL_LDC_CORE_HYBD_CHBUFF2_BA_L_ADDR_MASK, CSL_LDC_CORE_HYBD_CHBUFF2_BA_L_ADDR_SHIFT, CSL_LDC_CORE_HYBD_CHBUFF2_BA_L_ADDR_MAX },
{ "CSL_LSE_COMMON_CFG__ROW", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP_BASE + CSL_LSE_COMMON_CFG__ROW(0), CSL_LSE_COMMON_CFG__ROW_BPR0_MASK, CSL_LSE_COMMON_CFG__ROW_BPR0_SHIFT, CSL_LSE_COMMON_CFG__ROW_BPR0_MAX },
{ "CSL_LSE_DST_COMMON_CFG", CSL_VPAC0_PAR_VPAC_LDC0_S_VBUSP_VPAC_LDC_LSE_CFG_VP_BASE + CSL_LSE_DST_COMMON_CFG, CSL_LSE_DST_COMMON_CFG_ROUNDING_OFFSET_MASK, CSL_LSE_DST_COMMON_CFG_ROUNDING_OFFSET_SHIFT, CSL_LSE_DST_COMMON_CFG_ROUNDING_OFFSET_MAX },
// { "CSL_VISS_TOP_REVISION_REG", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_REVISION_REG, CSL_VISS_TOP_REVISION_REG_SCHEME_MASK, CSL_VISS_TOP_REVISION_REG_SCHEME_SHIFT, CSL_VISS_TOP_REVISION_REG_SCHEME_MAX },
// { "CSL_VISS_TOP_VISS_FUSE_STATUS", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_VISS_FUSE_STATUS, CSL_VISS_TOP_VISS_FUSE_STATUS_NIKON_DISABLE_MASK, CSL_VISS_TOP_VISS_FUSE_STATUS_NIKON_DISABLE_SHIFT, CSL_VISS_TOP_VISS_FUSE_STATUS_NIKON_DISABLE_MAX },
// { "CSL_VISS_TOP_VISS_LINEMEM_SIZE", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_VISS_LINEMEM_SIZE, CSL_VISS_TOP_VISS_LINEMEM_SIZE_LINEMEM_SZ_MASK, CSL_VISS_TOP_VISS_LINEMEM_SIZE_LINEMEM_SZ_SHIFT, CSL_VISS_TOP_VISS_LINEMEM_SIZE_LINEMEM_SZ_MAX },
{ "CSL_VISS_TOP_SYSCONFIG", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_SYSCONFIG, CSL_VISS_TOP_SYSCONFIG_CLKCG_OVERIDE_MASK, CSL_VISS_TOP_SYSCONFIG_CLKCG_OVERIDE_SHIFT, CSL_VISS_TOP_SYSCONFIG_CLKCG_OVERIDE_MAX },
{ "CSL_VISS_TOP_VISS_CNTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_VISS_CNTL, CSL_VISS_TOP_VISS_CNTL_CAC_EN_MASK, CSL_VISS_TOP_VISS_CNTL_CAC_EN_SHIFT, CSL_VISS_TOP_VISS_CNTL_CAC_EN_MAX },
{ "CSL_VISS_TOP_FREEPCLK_CFG", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_FREEPCLK_CFG, CSL_VISS_TOP_FREEPCLK_CFG_PCLKFREE_EN_MASK, CSL_VISS_TOP_FREEPCLK_CFG_PCLKFREE_EN_SHIFT, CSL_VISS_TOP_FREEPCLK_CFG_PCLKFREE_EN_MAX },
{ "CSL_VISS_TOP_FCP2_CNTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_FCP2_CNTL, CSL_VISS_TOP_FCP2_CNTL_IN_PIPEDLY_MASK, CSL_VISS_TOP_FCP2_CNTL_IN_PIPEDLY_SHIFT, CSL_VISS_TOP_FCP2_CNTL_IN_PIPEDLY_MAX },
{ "CSL_VISS_TOP_LSEOUT_MUX_CNTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_LSEOUT_MUX_CNTL, CSL_VISS_TOP_LSEOUT_MUX_CNTL_Y12SEL_MASK, CSL_VISS_TOP_LSEOUT_MUX_CNTL_Y12SEL_SHIFT, CSL_VISS_TOP_LSEOUT_MUX_CNTL_Y12SEL_MAX },
{ "CSL_VISS_TOP_VISS_DBG_CTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_VISS_DBG_CTL, CSL_VISS_TOP_VISS_DBG_CTL_PRTL_WR_EN_MASK, CSL_VISS_TOP_VISS_DBG_CTL_PRTL_WR_EN_SHIFT, CSL_VISS_TOP_VISS_DBG_CTL_PRTL_WR_EN_MAX },
{ "CSL_VISS_TOP_VISS_DBG_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_VISS_DBG_STAT, CSL_VISS_TOP_VISS_DBG_STAT_PRTL_WR_MASK, CSL_VISS_TOP_VISS_DBG_STAT_PRTL_WR_SHIFT, CSL_VISS_TOP_VISS_DBG_STAT_PRTL_WR_MAX },
{ "CSL_VISS_TOP_GLBCECONFIG", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_GLBCECONFIG, CSL_VISS_TOP_GLBCECONFIG_GLBCE_PCLKFREE_MASK, CSL_VISS_TOP_GLBCECONFIG_GLBCE_PCLKFREE_SHIFT, CSL_VISS_TOP_GLBCECONFIG_GLBCE_PCLKFREE_MAX },
{ "CSL_VISS_TOP_GLBCE_VPSYNCDLY", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_GLBCE_VPSYNCDLY, CSL_VISS_TOP_GLBCE_VPSYNCDLY_V_DLY_MASK, CSL_VISS_TOP_GLBCE_VPSYNCDLY_V_DLY_SHIFT, CSL_VISS_TOP_GLBCE_VPSYNCDLY_V_DLY_MAX },
{ "CSL_VISS_TOP_GLBCE_INT_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_GLBCE_INT_STAT, CSL_VISS_TOP_GLBCE_INT_STAT_VSYNC_ERR_MASK, CSL_VISS_TOP_GLBCE_INT_STAT_VSYNC_ERR_SHIFT, CSL_VISS_TOP_GLBCE_INT_STAT_VSYNC_ERR_MAX },
{ "CSL_VISS_TOP_GLBCE_DBG_CTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_GLBCE_DBG_CTL, CSL_VISS_TOP_GLBCE_DBG_CTL_EOF_EN_MASK, CSL_VISS_TOP_GLBCE_DBG_CTL_EOF_EN_SHIFT, CSL_VISS_TOP_GLBCE_DBG_CTL_EOF_EN_MAX },
{ "CSL_VISS_TOP_GLBCE_DBG_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_GLBCE_DBG_STAT, CSL_VISS_TOP_GLBCE_DBG_STAT_EOF_MASK, CSL_VISS_TOP_GLBCE_DBG_STAT_EOF_SHIFT, CSL_VISS_TOP_GLBCE_DBG_STAT_EOF_MAX },
{ "CSL_VISS_TOP_NSF4V_INT_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_NSF4V_INT_STAT, CSL_VISS_TOP_NSF4V_INT_STAT_VBLANK_ERR_MASK, CSL_VISS_TOP_NSF4V_INT_STAT_VBLANK_ERR_SHIFT, CSL_VISS_TOP_NSF4V_INT_STAT_VBLANK_ERR_MAX },
{ "CSL_VISS_TOP_NSF4V_DBG_CTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_NSF4V_DBG_CTL, CSL_VISS_TOP_NSF4V_DBG_CTL_EOF_EN_MASK, CSL_VISS_TOP_NSF4V_DBG_CTL_EOF_EN_SHIFT, CSL_VISS_TOP_NSF4V_DBG_CTL_EOF_EN_MAX },
{ "CSL_VISS_TOP_NSF4V_DBG_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_NSF4V_DBG_STAT, CSL_VISS_TOP_NSF4V_DBG_STAT_EOF_MASK, CSL_VISS_TOP_NSF4V_DBG_STAT_EOF_SHIFT, CSL_VISS_TOP_NSF4V_DBG_STAT_EOF_MAX },
{ "CSL_VISS_TOP_DBGEVT_CTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_DBGEVT_CTL, CSL_VISS_TOP_DBGEVT_CTL_SEL1_MASK, CSL_VISS_TOP_DBGEVT_CTL_SEL1_SHIFT, CSL_VISS_TOP_DBGEVT_CTL_SEL1_MAX },
{ "CSL_VISS_TOP_TEST_CNTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_MMR_CFG_VISS_TOP_BASE + CSL_VISS_TOP_TEST_CNTL, CSL_VISS_TOP_TEST_CNTL_GATED_MEM_CLKF_MASK, CSL_VISS_TOP_TEST_CNTL_GATED_MEM_CLKF_SHIFT, CSL_VISS_TOP_TEST_CNTL_GATED_MEM_CLKF_MAX },
{ "CSL_CAC_CTRL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_CTRL, CSL_CAC_CTRL_COLOR_EN_MASK, CSL_CAC_CTRL_COLOR_EN_SHIFT, CSL_CAC_CTRL_COLOR_EN_MAX },
{ "CSL_CAC_FRAMESZ", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_FRAMESZ, CSL_CAC_FRAMESZ_WIDTH_MASK, CSL_CAC_FRAMESZ_WIDTH_SHIFT, CSL_CAC_FRAMESZ_WIDTH_MAX },
{ "CSL_CAC_BLOCKSZ", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_BLOCKSZ, CSL_CAC_BLOCKSZ_SIZE_MASK, CSL_CAC_BLOCKSZ_SIZE_SHIFT, CSL_CAC_BLOCKSZ_SIZE_MAX },
{ "CSL_CAC_BLOCKCNT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_BLOCKCNT, CSL_CAC_BLOCKCNT_HCNT_MASK, CSL_CAC_BLOCKCNT_HCNT_SHIFT, CSL_CAC_BLOCKCNT_HCNT_MAX },
{ "CSL_CAC_INT_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_INT_STAT, CSL_CAC_INT_STAT_LUT_CFG_ERR_MASK, CSL_CAC_INT_STAT_LUT_CFG_ERR_SHIFT, CSL_CAC_INT_STAT_LUT_CFG_ERR_MAX },
{ "CSL_CAC_DBG_CTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_DBG_CTL, CSL_CAC_DBG_CTL_LINEMEM_SEL_MASK, CSL_CAC_DBG_CTL_LINEMEM_SEL_SHIFT, CSL_CAC_DBG_CTL_LINEMEM_SEL_MAX },
{ "CSL_CAC_DBG_STAT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_CAC_S_VBUSP_MMRCFG_CAC_BASE + CSL_CAC_DBG_STAT, CSL_CAC_DBG_STAT_EOF_MASK, CSL_CAC_DBG_STAT_EOF_SHIFT, CSL_CAC_DBG_STAT_EOF_MAX },
{ "CSL_FLEXCFA_LUT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_LUT(0), CSL_FLEXCFA_LUT_LUT_ENTRY_LO_MASK, CSL_FLEXCFA_LUT_LUT_ENTRY_LO_SHIFT, CSL_FLEXCFA_LUT_LUT_ENTRY_LO_MAX },
{ "CSL_FLEXCFA_CFG_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CFG_0, CSL_FLEXCFA_CFG_0_HEIGHT_MASK, CSL_FLEXCFA_CFG_0_HEIGHT_SHIFT, CSL_FLEXCFA_CFG_0_HEIGHT_MAX },
{ "CSL_FLEXCFA_CFG_1", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CFG_1, CSL_FLEXCFA_CFG_1_BYPASS_CORE3_MASK, CSL_FLEXCFA_CFG_1_BYPASS_CORE3_SHIFT, CSL_FLEXCFA_CFG_1_BYPASS_CORE3_MAX },
{ "CSL_FLEXCFA_CORE_DIR_PHASE_ROW_COL_COEF", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CORE_DIR_PHASE_ROW_COL_COEF(0, 0, 0, 0, 0), CSL_FLEXCFA_CORE_DIR_PHASE_ROW_COL_COEF_COEF_0_MASK, CSL_FLEXCFA_CORE_DIR_PHASE_ROW_COL_COEF_COEF_0_SHIFT, CSL_FLEXCFA_CORE_DIR_PHASE_ROW_COL_COEF_COEF_0_MAX },
{ "CSL_FLEXCFA_GRAD_CFG", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_GRAD_CFG, CSL_FLEXCFA_GRAD_CFG_BLENDMODECORE3_MASK, CSL_FLEXCFA_GRAD_CFG_BLENDMODECORE3_SHIFT, CSL_FLEXCFA_GRAD_CFG_BLENDMODECORE3_MAX },
{ "CSL_FLEXCFA_SET0_GRAD_HZ", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_GRAD_HZ, CSL_FLEXCFA_SET0_GRAD_HZ_PHASE3_MASK, CSL_FLEXCFA_SET0_GRAD_HZ_PHASE3_SHIFT, CSL_FLEXCFA_SET0_GRAD_HZ_PHASE3_MAX },
{ "CSL_FLEXCFA_SET0_GRAD_VT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_GRAD_VT, CSL_FLEXCFA_SET0_GRAD_VT_PHASE3_MASK, CSL_FLEXCFA_SET0_GRAD_VT_PHASE3_SHIFT, CSL_FLEXCFA_SET0_GRAD_VT_PHASE3_MAX },
{ "CSL_FLEXCFA_SET0_INTENSITY0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_INTENSITY0, CSL_FLEXCFA_SET0_INTENSITY0_SHIFT_PH1_MASK, CSL_FLEXCFA_SET0_INTENSITY0_SHIFT_PH1_SHIFT, CSL_FLEXCFA_SET0_INTENSITY0_SHIFT_PH1_MAX },
{ "CSL_FLEXCFA_SET0_INTENSITY1", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_INTENSITY1, CSL_FLEXCFA_SET0_INTENSITY1_SHIFT_PH3_MASK, CSL_FLEXCFA_SET0_INTENSITY1_SHIFT_PH3_SHIFT, CSL_FLEXCFA_SET0_INTENSITY1_SHIFT_PH3_MAX },
{ "CSL_FLEXCFA_SET1_GRAD_HZ", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_GRAD_HZ, CSL_FLEXCFA_SET1_GRAD_HZ_PHASE3_MASK, CSL_FLEXCFA_SET1_GRAD_HZ_PHASE3_SHIFT, CSL_FLEXCFA_SET1_GRAD_HZ_PHASE3_MAX },
{ "CSL_FLEXCFA_SET1_GRAD_VT", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_GRAD_VT, CSL_FLEXCFA_SET1_GRAD_VT_PHASE3_MASK, CSL_FLEXCFA_SET1_GRAD_VT_PHASE3_SHIFT, CSL_FLEXCFA_SET1_GRAD_VT_PHASE3_MAX },
{ "CSL_FLEXCFA_SET1_INTENSITY0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_INTENSITY0, CSL_FLEXCFA_SET1_INTENSITY0_SHIFT_PH1_MASK, CSL_FLEXCFA_SET1_INTENSITY0_SHIFT_PH1_SHIFT, CSL_FLEXCFA_SET1_INTENSITY0_SHIFT_PH1_MAX },
{ "CSL_FLEXCFA_SET1_INTENSITY1", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_INTENSITY1, CSL_FLEXCFA_SET1_INTENSITY1_SHIFT_PH3_MASK, CSL_FLEXCFA_SET1_INTENSITY1_SHIFT_PH3_SHIFT, CSL_FLEXCFA_SET1_INTENSITY1_SHIFT_PH3_MAX },
{ "CSL_FLEXCFA_SET0_THR0_1", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_THR0_1, CSL_FLEXCFA_SET0_THR0_1_THR_1_MASK, CSL_FLEXCFA_SET0_THR0_1_THR_1_SHIFT, CSL_FLEXCFA_SET0_THR0_1_THR_1_MAX },
{ "CSL_FLEXCFA_SET0_THR2_3", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_THR2_3, CSL_FLEXCFA_SET0_THR2_3_THR_3_MASK, CSL_FLEXCFA_SET0_THR2_3_THR_3_SHIFT, CSL_FLEXCFA_SET0_THR2_3_THR_3_MAX },
{ "CSL_FLEXCFA_SET0_THR4_5", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_THR4_5, CSL_FLEXCFA_SET0_THR4_5_THR_5_MASK, CSL_FLEXCFA_SET0_THR4_5_THR_5_SHIFT, CSL_FLEXCFA_SET0_THR4_5_THR_5_MAX },
{ "CSL_FLEXCFA_SET0_THR6", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET0_THR6, CSL_FLEXCFA_SET0_THR6_THR_6_MASK, CSL_FLEXCFA_SET0_THR6_THR_6_SHIFT, CSL_FLEXCFA_SET0_THR6_THR_6_MAX },
{ "CSL_FLEXCFA_SET1_THR0_1", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_THR0_1, CSL_FLEXCFA_SET1_THR0_1_THR_1_MASK, CSL_FLEXCFA_SET1_THR0_1_THR_1_SHIFT, CSL_FLEXCFA_SET1_THR0_1_THR_1_MAX },
{ "CSL_FLEXCFA_SET1_THR2_3", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_THR2_3, CSL_FLEXCFA_SET1_THR2_3_THR_3_MASK, CSL_FLEXCFA_SET1_THR2_3_THR_3_SHIFT, CSL_FLEXCFA_SET1_THR2_3_THR_3_MAX },
{ "CSL_FLEXCFA_SET1_THR4_5", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_THR4_5, CSL_FLEXCFA_SET1_THR4_5_THR_5_MASK, CSL_FLEXCFA_SET1_THR4_5_THR_5_SHIFT, CSL_FLEXCFA_SET1_THR4_5_THR_5_MAX },
{ "CSL_FLEXCFA_SET1_THR6", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_SET1_THR6, CSL_FLEXCFA_SET1_THR6_THR_6_MASK, CSL_FLEXCFA_SET1_THR6_THR_6_SHIFT, CSL_FLEXCFA_SET1_THR6_THR_6_MAX },
{ "CSL_FLEXCFA_INT_STATUS", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_INT_STATUS, CSL_FLEXCFA_INT_STATUS_LUT_CFG_ERR_MASK, CSL_FLEXCFA_INT_STATUS_LUT_CFG_ERR_SHIFT, CSL_FLEXCFA_INT_STATUS_LUT_CFG_ERR_MAX },
{ "CSL_FLEXCFA_DEBUG_CTL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_DEBUG_CTL, CSL_FLEXCFA_DEBUG_CTL_SOF_EN_MASK, CSL_FLEXCFA_DEBUG_CTL_SOF_EN_SHIFT, CSL_FLEXCFA_DEBUG_CTL_SOF_EN_MAX },
{ "CSL_FLEXCFA_DEBUG_STATUS", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_DEBUG_STATUS, CSL_FLEXCFA_DEBUG_STATUS_SOF_EVENT_MASK, CSL_FLEXCFA_DEBUG_STATUS_SOF_EVENT_SHIFT, CSL_FLEXCFA_DEBUG_STATUS_SOF_EVENT_MAX },
{ "CSL_FLEXCFA_LINE_SEL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_LINE_SEL, CSL_FLEXCFA_LINE_SEL_LINE_SELECTOR_MASK, CSL_FLEXCFA_LINE_SEL_LINE_SELECTOR_SHIFT, CSL_FLEXCFA_LINE_SEL_LINE_SELECTOR_MAX },
{ "CSL_FLEXCFA_DANDC_COM_CTRL", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_DANDC_COM_CTRL, CSL_FLEXCFA_DANDC_COM_CTRL_DISFIR3_MASK, CSL_FLEXCFA_DANDC_COM_CTRL_DISFIR3_SHIFT, CSL_FLEXCFA_DANDC_COM_CTRL_DISFIR3_MAX },
{ "CSL_FLEXCFA_CCM_OCH0_ICH1_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH0_ICH1_0, CSL_FLEXCFA_CCM_OCH0_ICH1_0_CCM_OCH0_ICH1_MASK, CSL_FLEXCFA_CCM_OCH0_ICH1_0_CCM_OCH0_ICH1_SHIFT, CSL_FLEXCFA_CCM_OCH0_ICH1_0_CCM_OCH0_ICH1_MAX },
{ "CSL_FLEXCFA_CCM_OCH0_ICH3_2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH0_ICH3_2, CSL_FLEXCFA_CCM_OCH0_ICH3_2_CCM_OCH0_ICH3_MASK, CSL_FLEXCFA_CCM_OCH0_ICH3_2_CCM_OCH0_ICH3_SHIFT, CSL_FLEXCFA_CCM_OCH0_ICH3_2_CCM_OCH0_ICH3_MAX },
{ "CSL_FLEXCFA_CCM_OCH0_OFFSET", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH0_OFFSET, CSL_FLEXCFA_CCM_OCH0_OFFSET_CCM_OCH0_OFFSET_MASK, CSL_FLEXCFA_CCM_OCH0_OFFSET_CCM_OCH0_OFFSET_SHIFT, CSL_FLEXCFA_CCM_OCH0_OFFSET_CCM_OCH0_OFFSET_MAX },
{ "CSL_FLEXCFA_CCM_OCH1_ICH1_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH1_ICH1_0, CSL_FLEXCFA_CCM_OCH1_ICH1_0_CCM_OCH1_ICH1_MASK, CSL_FLEXCFA_CCM_OCH1_ICH1_0_CCM_OCH1_ICH1_MAX, CSL_FLEXCFA_CCM_OCH1_ICH1_0_CCM_OCH1_ICH1_MAX },
{ "CSL_FLEXCFA_CCM_OCH1_ICH3_2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH1_ICH3_2, CSL_FLEXCFA_CCM_OCH1_ICH3_2_CCM_OCH1_ICH3_MASK, CSL_FLEXCFA_CCM_OCH1_ICH3_2_CCM_OCH1_ICH3_SHIFT, CSL_FLEXCFA_CCM_OCH1_ICH3_2_CCM_OCH1_ICH3_MAX },
{ "CSL_FLEXCFA_CCM_OCH1_OFFSET", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH1_OFFSET, CSL_FLEXCFA_CCM_OCH1_OFFSET_CCM_OCH1_OFFSET_MASK, CSL_FLEXCFA_CCM_OCH1_OFFSET_CCM_OCH1_OFFSET_SHIFT, CSL_FLEXCFA_CCM_OCH1_OFFSET_CCM_OCH1_OFFSET_MAX },
{ "CSL_FLEXCFA_CCM_OCH2_ICH1_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH2_ICH1_0, CSL_FLEXCFA_CCM_OCH2_ICH1_0_CCM_OCH2_ICH1_MASK, CSL_FLEXCFA_CCM_OCH2_ICH1_0_CCM_OCH2_ICH1_SHIFT, CSL_FLEXCFA_CCM_OCH2_ICH1_0_CCM_OCH2_ICH1_MAX },
{ "CSL_FLEXCFA_CCM_OCH2_ICH3_2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH2_ICH3_2, CSL_FLEXCFA_CCM_OCH2_ICH3_2_CCM_OCH2_ICH3_MASK, CSL_FLEXCFA_CCM_OCH2_ICH3_2_CCM_OCH2_ICH3_SHIFT, CSL_FLEXCFA_CCM_OCH2_ICH3_2_CCM_OCH2_ICH3_MAX },
{ "CSL_FLEXCFA_CCM_OCH2_OFFSET", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH2_OFFSET, CSL_FLEXCFA_CCM_OCH2_OFFSET_CCM_OCH2_OFFSET_MASK, CSL_FLEXCFA_CCM_OCH2_OFFSET_CCM_OCH2_OFFSET_SHIFT, CSL_FLEXCFA_CCM_OCH2_OFFSET_CCM_OCH2_OFFSET_MAX },
{ "CSL_FLEXCFA_CCM_OCH3_ICH1_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH3_ICH1_0, CSL_FLEXCFA_CCM_OCH3_ICH1_0_CCM_OCH3_ICH1_MASK, CSL_FLEXCFA_CCM_OCH3_ICH1_0_CCM_OCH3_ICH1_SHIFT, CSL_FLEXCFA_CCM_OCH3_ICH1_0_CCM_OCH3_ICH1_MAX },
{ "CSL_FLEXCFA_CCM_OCH3_ICH3_2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH3_ICH3_2, CSL_FLEXCFA_CCM_OCH3_ICH3_2_CCM_OCH3_ICH3_MASK, CSL_FLEXCFA_CCM_OCH3_ICH3_2_CCM_OCH3_ICH3_SHIFT, CSL_FLEXCFA_CCM_OCH3_ICH3_2_CCM_OCH3_ICH3_MAX },
{ "CSL_FLEXCFA_CCM_OCH3_OFFSET", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CCM_OCH3_OFFSET, CSL_FLEXCFA_CCM_OCH3_OFFSET_CCM_OCH3_OFFSET_MASK, CSL_FLEXCFA_CCM_OCH3_OFFSET_CCM_OCH3_OFFSET_SHIFT, CSL_FLEXCFA_CCM_OCH3_OFFSET_CCM_OCH3_OFFSET_MAX },
{ "CSL_FLEXCFA_FIR_SCALES_1_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_FIR_SCALES_1_0, CSL_FLEXCFA_FIR_SCALES_1_0_FIR_SCALER1_MASK, CSL_FLEXCFA_FIR_SCALES_1_0_FIR_SCALER1_SHIFT, CSL_FLEXCFA_FIR_SCALES_1_0_FIR_SCALER1_MAX },
{ "CSL_FLEXCFA_FIR_SCALES_3_2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_FIR_SCALES_3_2, CSL_FLEXCFA_FIR_SCALES_3_2_FIR_SCALER3_MASK, CSL_FLEXCFA_FIR_SCALES_3_2_FIR_SCALER3_SHIFT, CSL_FLEXCFA_FIR_SCALES_3_2_FIR_SCALER3_MAX },
{ "CSL_FLEXCFA_FIR_OFFSETS_1_0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_FIR_OFFSETS_1_0, CSL_FLEXCFA_FIR_OFFSETS_1_0_FIR_OFFSET1_MASK, CSL_FLEXCFA_FIR_OFFSETS_1_0_FIR_OFFSET1_SHIFT, CSL_FLEXCFA_FIR_OFFSETS_1_0_FIR_OFFSET1_MAX },
{ "CSL_FLEXCFA_FIR_OFFSETS_3_2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_FIR_OFFSETS_3_2, CSL_FLEXCFA_FIR_OFFSETS_3_2_FIR_OFFSET3_MASK, CSL_FLEXCFA_FIR_OFFSETS_3_2_FIR_OFFSET3_SHIFT, CSL_FLEXCFA_FIR_OFFSETS_3_2_FIR_OFFSET3_MAX },
{ "CSL_FLEXCFA_CLUT0", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CLUT0(0), CSL_FLEXCFA_CLUT0_LUT_ENTRY_LO_MASK, CSL_FLEXCFA_CLUT0_LUT_ENTRY_LO_SHIFT, CSL_FLEXCFA_CLUT0_LUT_ENTRY_LO_MAX },
{ "CSL_FLEXCFA_CLUT1", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CLUT1(0), CSL_FLEXCFA_CLUT1_LUT_ENTRY_LO_MASK, CSL_FLEXCFA_CLUT0_LUT_ENTRY_LO_SHIFT, CSL_FLEXCFA_CLUT1_LUT_ENTRY_LO_MAX },
{ "CSL_FLEXCFA_CLUT2", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CLUT2(0), CSL_FLEXCFA_CLUT2_LUT_ENTRY_LO_MASK, CSL_FLEXCFA_CLUT2_LUT_ENTRY_LO_SHIFT, CSL_FLEXCFA_CLUT2_LUT_ENTRY_LO_MAX },
{ "CSL_FLEXCFA_CLUT3", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_CLUT3(0), CSL_FLEXCFA_CLUT3_LUT_ENTRY_LO_MASK, CSL_FLEXCFA_CLUT3_LUT_ENTRY_LO_SHIFT, CSL_FLEXCFA_CLUT3_LUT_ENTRY_LO_MAX },
{ "CSL_FLEXCFA_PIXEL_RAM", CSL_VPAC0_PAR_VPAC_VISS0_S_VBUSP_VISS_FCP2_CFA_VBUSP_FLEXCFA_BASE + CSL_FLEXCFA_PIXEL_RAM(0), CSL_FLEXCFA_PIXEL_RAM_PIXEL_LO_MASK, CSL_FLEXCFA_PIXEL_RAM_PIXEL_LO_SHIFT, CSL_FLEXCFA_PIXEL_RAM_PIXEL_LO_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_3, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_3_ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_3_ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_3_ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_MAX },
//// { "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_3, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_3_ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_3_ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_3_ENABLE_LEVEL_VPAC_OUT_0_EN_PIPE_DONE_0_CLR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_0, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_0_ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_0_ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_0_0_ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0_ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0_ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_0_0_ENABLE_LEVEL_VPAC_OUT_0_EN_VISS0_CR_CFG_ERR_CLR_MAX },
//// { "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_3, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_3_ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_3_ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_3_ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_MAX },
//// { "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_3, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_3_ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_3_ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_3_ENABLE_LEVEL_VPAC_OUT_1_EN_PIPE_DONE_0_CLR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_0, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_0_ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_0_ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_1_0_ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0_ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0_ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_1_0_ENABLE_LEVEL_VPAC_OUT_1_EN_VISS0_CR_CFG_ERR_CLR_MAX },
//// { "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_3, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_3_ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_3_ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_3_ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_3, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_3_ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_3_ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_3_ENABLE_LEVEL_VPAC_OUT_2_EN_PIPE_DONE_0_CLR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_0, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_0_ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_0_ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_2_0_ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0_ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0_ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_2_0_ENABLE_LEVEL_VPAC_OUT_2_EN_VISS0_CR_CFG_ERR_CLR_MAX },
//// { "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_3, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_3_ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_3_ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_3_ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_3", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_3, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_3_ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_3_ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_3_ENABLE_LEVEL_VPAC_OUT_4_EN_PIPE_DONE_0_CLR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_0, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_0_ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_MASK, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_0_ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_REG_LEVEL_VPAC_OUT_4_0_ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_MAX },
{ "CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0", CSL_VPAC0_CP_INTD_CFG_INTD_CFG_BASE + CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0_ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR_MASK, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0_ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR_SHIFT, CSL_VPAC_INTD_CFG_ENABLE_CLR_REG_LEVEL_VPAC_OUT_4_0_ENABLE_LEVEL_VPAC_OUT_4_EN_VISS0_CR_CFG_ERR_CLR_MAX },
can you please share the possible reason and is any optimized way to read above registers ?
Thanks
