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AM62P: PSI-L source thread for CPSW3G with two mac run in parallel

Changxing Du
Prodigy 80 points
Part Number: AM62P

Tool/software:

Hello 

In Linux SDK,

Only one DMA channel is configured for rx, we have two mac ports, does the CPSW3G support 2 sperate DMA channels for Rx with two sperate PSI-L threads repectively?

B.R.

Changxing DU

  • 0
    TI__Genius 16115 points

    Hi Changxing, 

    Can you check the results of "ethtool -l <interface name>" to see how many RX and TX channels is available?

    I believe this should indicate that CPSW3G is only able to support 1 RX channel. However, I'm learning that CPSW has something called "RX flows (upto 16 flows per channel on Sitara SoCs). Each flow has dedicated desc ring and dedicated IRQ which allows to CPSW HW to steer a received packet to a particular ring and thus a particular CPU (to which IRQ affinity is mapped to)". 

    Please let us know if you have additional questions.

    -Daolin

  • 0 in reply to Daolin Qiu
    Prodigy 80 points

    Hello Daoblin

    How can we configure it? because once the rx source thread is reqested by Mcu, the uboot or linux will not be able to register it.

    Do you have any hints on how to configure the flow and ring on both mcal (MCU R5) and linux side (A53)? This is done by one core or by seperate cores?

    B.R.

    Changxing Du

  • 0 in reply to Changxing Du
    TI__Genius 16115 points

    Hello Changxing, 

    Apologies for the delayed response.

    Daolin Qiu said:
    Can you check the results of "ethtool -l <interface name>" to see how many RX and TX channels is available?

    Were you able to check the results of this command?

    I found out that CPSW has a preset maximum of 8 RX channels however by default the hardware settings is set to 1 RX channel if you check "ethtool -l eth0" on the AM64x EVM. I assume something similar results for AM62Px TI EVM. 

    With some experimentation I could set the hardware settings to 8 RX channels with "ethtool -L eth0 rx 8", making sure that eth0 is brought down before setting this. See below log. I believe this is due to this patch: https://lore.kernel.org/all/20240703-am65-cpsw-multi-rx-v3-0-f11cd860fd72@kernel.org/ 

    root@am64xx-evm:~# ethtool -l eth0
Channel parameters for eth0:
Pre-set maximums:
RX:       8
TX:       8
Other:     n/a
Combined:    n/a
Current hardware settings:
RX:       1
TX:       8
Other:     n/a
Combined:    n/a
root@am64xx-evm:~# ip link set dev eth0 down
[ 1030.925065] am65-cpsw-nuss 8000000.ethernet eth0: Link is Down
root@am64xx-evm:~# ethtool -L eth0 rx 8
[ 1042.528606] am65-cpsw-nuss 8000000.ethernet: set new flow-id-base 16
root@am64xx-evm:~# ip link set dev eth0 up
[ 1055.718707] am65-cpsw-nuss 8000000.ethernet eth0: PHY [8000f00.mdio:00] driver [TI DP83867] (irq)
[ 1055.718739] am65-cpsw-nuss 8000000.ethernet eth0: configuring for phy/rgmii-rxid link mode
root@am64xx-evm:~# [ 1058.789119] am65-cpsw-nuss 8000000.ethernet eth0: Link is Up - 1Gbps/Full - fx

root@am64xx-evm:~# ethtool -l eth0
Channel parameters for eth0:
Pre-set maximums:
RX:       8
TX:       8
Other:     n/a
Combined:    n/a
Current hardware settings:
RX:       8
TX:       8
Other:     n/a
Combined:    n/a
root@am64xx-evm:~# uname -a
Linux am64xx-evm 6.12.35-gf462b01e9ac7-dirty #7 SMP PREEMPT_RT Fri Aug 22 14:20:37 CDT 2025 aarch64x
root@am64xx-evm:~#

    Would this multi RX queue feature be something that you are able to apply for your use-case?

    -Daolin

  • 0 in reply to Daolin Qiu
    Prodigy 80 points

    Hello Daolin

    Thanks for your info. But the eth tool can only be used under linux.

    We want to share the same Rx fifo by Mcu (Mcal will be run) and A53 (Linux core).

    So the issue is that how we change the SDK?

    In the current Linux SDK, there is only one Rx channel with one thread supported. And will confilict with Mcal side.

  • 0 in reply to Changxing Du
    TI__Intellectual 2810 points

    Hello Changzing,

    There is a way to share network traffic between multiple cores in am62p. It is through Ethernet Firmware (EthFw) support that comes as part of am62px MCU+ SDK. We don't exactly share the fifo, configure DMA channels in a way that both Linux and MCAL have access to the CPSW peripheral. But the control of peripheral is with wkup-r5. 

    There are few considerations to be taken. 

    1. The configuration and control of CPSW is maintained within wkup-R5 core, and other cores will have IPC based messaging with wkup-r5 to communicate required peripheral config changes.
    2. Shared multicast (multicast address to which more than one cores are registered to, in the system of 3 cores) and broadcast traffic needs special handling. This is currently supported via a shared memory based interface, and Cdd for the same is not currently part of our MCAL offering. This has to be implemented if the above 2 classes of traffic are needed

    Please let me know if there are any queries regarding the support, or functionalities of EthFw.

    Regards,
    Teja.

  • 0 in reply to Teja Rowthu
    Prodigy 80 points

    Hello Teja,

    Thanks for your support. Could you please share some performance test result when use IPC?

    B.R.

    Changxing

  • 0 in reply to Changxing Du
    TI__Intellectual 2810 points

    Hello Changzing,

    Do you mean to say performance results when the data sharing is done through IPC instead of EthFw mentioned above?

    Regards,
    Teja.