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AM62L: Impedance requirements for LPDDR4 signals

Jaydip Vadodariya
Prodigy 100 points
Part Number: AM62L

Tool/software:

Hi TI Team,

We are currently designing a custom board using the AM62L processor with LPDDR4 memory and have noticed discrepancies in the impedance requirements for LPDDR4 signal routing.

  1. In the EVM schematic, the specified impedance is:

    • 66Ω for LPDDR4_CK_P/N

    • 80Ω for LPDDR4_DQSx_P/N

  2. However, in the EVM layout, the routing follows:

    • 100Ω differential

    • 50Ω single-ended

  3. In the LPDDR4 Routing Guidelines document, the recommendation is:

    • 80Ω differential

    • 40Ω single-ended

We have attached screenshots from the schematic, layout, and the routing guideline document for your reference.

Could you please confirm which impedance values we should follow for our custom board to ensure signal integrity.

Looking forward to your guidance.

Best regards,
Jaydip

  • 0
    TI__Guru* 86160 points

    The DDR guidelines app note parameters are "typical" so you can vary these, but i would recommend proper power aware board simulations to prove out signal integrity.

    I wasn't aware of the discrepancy with the schematic vs. layout, let me check.

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 100 points

    Hi James,

    Thank you for your response.

    Please review the guidelines and confirm the correct impedance requirements so that we can proceed with the layout.

    Regards,

    Jaydip  

  • 0 in reply to Jaydip Vadodariya
    Prodigy 100 points

    Hi James,

    Could you please confirm the typical impedance requirements so we can move forward with the layout?

    Regards,

    Jaydip  

  • +1 in reply to Jaydip Vadodariya
    TI__Guru* 86160 points

    Hi Jaydip, impedances of 40-50ohms SE and 80-100ohms differential are typical.  We list 40/80 as typical in the app note, but several customers have used 50/100.  I did confirm, as you pointed out, we used 50/100 on the EVM.  

    Regards,

    James

  • 0 in reply to JJD
    Prodigy 110 points
    We’re routing AM62L + LPDDR4 and ran into a practical constraint with the 40Ω SE / 80Ω Diff recommendation from the app note.
    Context
    • TI feedback from James: “Impedances of 40–50Ω single-ended and 80–100Ω differential are typical. We list 40/80 as typical in the app note, but several customers have used 50/100. I did confirm we used 50/100 on the EVM.”
    • On our stack-up, achieving 40/80 requires ~6.80 mil trace width; with that width, maintaining even 1W pair-to-pair separation becomes challenging in dense areas.
    • With 50/100, a ~4.20 mil trace is feasible and we can maintain ≥1.5W spacing consistently, similar to the EVM.
    Proposal
    Proceed with 50Ω single-ended / 100Ω differential for:
    • LPDDR4_CK_P/N and DQSx_P/N (100Ω diff),
    • All LPDDR4 single-ended signals (50Ω SE: ADDR/CTRL/DQ, etc.).
    Checks/asks
    1. Please confirm no special IO/ODT setting changes are required on AM62L for 50/100 versus 40/80 (we assume standard EVM settings are valid).
    1. Any nets that TI prefers to keep strictly at 40/80 for margin reasons? (Our plan is 50/100 across the LPDDR4 interface for consistency.)
    2. We will still meet standard LPDDR4 constraints:
      • CK/DQS intra-pair and inter-byte skew budgets per AM62L guidelines,
      • Length matching within byte lanes,
      • ≥1W spacing for crosstalk control, solid reference plane continuity, and via count minimization.
    If there are no objections, we’ll proceed with 50/100 to ensure manufacturability and spacing while aligning with the EVM.
  • 0 in reply to Fenil Ladani
    TI__Guru* 86160 points

    1. Not necessarily.  You may need to change drive strength and termination settings for your board.  The values we use for the EVM are specific to that board

    2. No,  keep the consistency across the interface.  The processor and memory will have both ODI/ODT settings for the whole bus anyway, you don't want any impedance mismatches within each bus

    I don't see any issues.  Other than the 50/100 impedances, it sounds like you are following all of the guidelines in the app note (BTW, we plan on changing the app note better indicate that 50/100 is ok).   Will you be performing board level simulations?  This will give you better confidence for a successful design.

    Regards,

    James