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how to use delay line

Kee Yong Ting
Intellectual 310 points

Hi, I am implementing fir filter c6748 processor, but due to the size of the data to be process, those data is being buffered at the external ram. I have doing some setting in AMR register to enable the delay line, but there seems no speed improvement in my case. so, i would like to know if the delay line is enabled by default. By the way, I am quite blur about how the delay line in ti processor work. Does it move those data into the L2 cache and remain there until certain portion of data is being updated? Thank you.

  • 0
    Intellectual 370 points

    Hello,

     

    Which AMR register are you manipulating?

     

    When using external RAM (SDRAM or DDR), I always make sure that

    1) the external ram controller is set up for maximum speed,

    2) the L2 is set for all cache,

    3)enable all caches, and use the MARn registers to tell the cache controller that the external ram is cacheable.

     

    The cache controller is really very good at keeping the data in the L2 cache until the space is needed for something else.  If, however, your FIR is so long that the state vector doesn't fit in L2, you may need to try a different signal processing algorithm.  An algorithm that performs as much work on piece of memory before moving on to another will work better.

     

    On the other hand, if all you are doing is a delay line, or sparse FIR, where new data replaces old data in a sparse vector, the cache controller does a pretty good job reading in old data, allowing modifications, and then writing back after you're done changing it.

     

    See sprug82a.pdf for excellent description on the cache, and spruh79a.pdf, chapter 13 for DDR setup.  I usually try to follow the setup sequence in the gel file in CCS.

     

    Best Regards,

    Cameron

     

  • 0 in reply to kemeron
    TI__Guru* 84110 points

    Kee Yong Ting,

    If you are referring to a delay line implemented in one of our DSPLib FIR functions, please be specific about that. If you are talking about circular addressing, we would need to know that, so the chosen words are clear.

    If you are not using a FIR function from the DSPLib, please search TI.com for DSPLib and find the library for your DSP core, the C674x. It is compatible with the version for the C67+ DSP core, also, although the example files might require some work to port.

    Using the AMR register can cause significant issue with C code, so be very careful. The side effects may be very difficult to find and debug. I first recommend not using these, and I second recommend to disable interrupts before changing AMR, and then restore AMR before re-enabling interrupts. Even the use of the C language should be avoided while AMR is modified.

    The circular addressing modes implemented through AMR have no direct relationship to the use of cache. These are strictly addressing modes that affect how the selected registers are used for load/store and addressing instructions.

    Regards,
    RandyP