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TDA4VEN-Q1: LPDDR4 Design constraint

Part Number: TDA4VEN-Q1

Tool/software:

Hi. 

What is the allowable propagation delay difference between CLK and DQS?

In J722S, CLK: 1298.5mil, DQS3_P: 650.8mil is the shortest. Is it possible to tolerate a maximum allowable delay difference of 100 psec?

Regards,