I use a 6416. I use the 32 HPI bus. A FPGA is the host,the 6416 is slave . I can successfully write but failed to read back. The hrdy signal is wrong when I try to read back. Do I write some thing in dsp 6416 register like TRCTL before I use HPI bus? Most time The hrdy is low during read. If I reset the DSP manytimes,Sometime the hrdy seems good,
the follow is my code :the first one is write which is successful the second one is read which failed.
the first one :
module hpiface(sysclk,locked,hrdy,hint,rw,hds1,hds2,hcs,hcntl,hd);
output [31:0] hd;
input hrdy;
input hint;
input locked;
input sysclk;
output rw;
output hds1;
output hds2;
output hcs;
output [1:0] hcntl;
reg [31:0] hd;
reg [31:0] data;
reg hcs;
reg hds1;
reg hds2;
reg rw;
reg [1:0]hcntl;
reg [1:0]control;
reg [2:0]cnt;
reg [6:0]step;
reg over;
parameter HPIC=2'b00;// control HPI control register
parameter HPIA=2'b01;// address HPI address register
parameter HPIDS=2'b10;// successive write
parameter HPID=2'b11;// fix address write
parameter SETUP=7'b0000001;// state
parameter HSTROBE_ACTIVE=7'b0000010;
parameter WAITING_DATA=7'b0000100;
parameter HSTROBE_INACTIVE=7'b0001000;
parameter END_CHANGE=7'b0010000;
parameter EMPTY=7'b0100000;
parameter IDLE=7'b1000000;
/*parameter DPIC=32'h00080008;// control data
parameter DPIA=32'h018800d8;// address data
parameter DPID=32'h66666666;// write or read data */
wire ready;
wire plllocked;
assign ready=hrdy;
assign plllocked=locked;
always @ (posedge sysclk )
begin
if(plllocked)//PLL locked go
begin
case (step)
SETUP:
begin
rw<=0;
hcs<=0;
hds1<=0;
hds2<=0;
hcntl<=control;
step<=HSTROBE_ACTIVE;
end
HSTROBE_ACTIVE:
begin
hds2<=1;
step<=WAITING_DATA;
end
WAITING_DATA:
begin
if(ready==0)//ready is active write data
begin
hd<=data;
step<=HSTROBE_INACTIVE;
end
else
begin
step<=WAITING_DATA;
end
end
HSTROBE_INACTIVE:
begin
hds2<=0;
step<=END_CHANGE;
/*if(over==0)
begin
step<=END_CHANGE;
end
else
begin
step<=IDLE;
end*/
end
END_CHANGE:
begin
//hcs<=1;
step<=EMPTY;
if(cnt==3'b101)
begin
cnt<=3'b000;
over<=1;
end
else
begin
cnt<=cnt+1;
end
end
EMPTY:
begin
step<=SETUP;
end
IDLE:
begin
step<=IDLE;
end
default :
begin
step<=SETUP;
end
endcase
end
else// PLL unlock wait
begin
cnt<=3'b000;
step<=SETUP;
hcs<=1;
hds1<=0;
hds2<=0;
over<=0;
end
end
always @ (posedge sysclk)
begin
if(plllocked)
begin
if(cnt==3'b000)
begin
control<=2'b00;//HPIC
data<=32'h00080008;//DPIC;
end
else if(cnt==3'b001)
begin
control<=2'b01;//HPIA;
data<=32'h000e4844;//DPIA;
end
else if(cnt==3'b010)
begin
control<=2'b10;//HPID;
data<=32'h11111111;//DPID;
end
else if(cnt==3'b011)
begin
data<=32'h22222222;//DPID
end
else if(cnt==3'b100)
begin
data<=32'h33333333;//DPID
end
else if(cnt==3'b101)
begin
data<=32'h44444444;//DPID
end
else
begin
control<=2'b00;//HPIC;
data<=32'h00080008;//DPIC;
end
end
else
begin
control<=2'b00;//HPIC;
data<=32'h00080008;//DPIC;
end
end
endmodule
the second one :
module hpiface(sysclk,locked,hrdy,hint,rw,hds1,hds2,hcs,hcntl,hd,tdata,step,dspreset);
inout [31:0] hd;
input hrdy;
input hint;
input locked;
input sysclk;
output rw;
output hds1;
output hds2;
output hcs;
output [1:0] hcntl;
output [31:0] tdata;
output dspreset;
reg [31:0] tdata;
reg [31:0] hd_reg;
reg [31:0] data;
reg [31:0] data1;
reg hcs;
reg hds1;
reg hds2;
reg rw;
reg wrcontrol;
reg dspreset;
reg [1:0]hcntl;
reg [1:0]control;
reg [2:0]cnt;
reg [27:0]cnt2;
output reg [7:0]step;
parameter HPIC=2'b00;// control HPI control register
parameter HPIA=2'b01;// address HPI address register
parameter HPIDS=2'b10;// autoincrement
parameter HPID=2'b11;// fix address write
/*parameter SETUP=7'b0000001;// state
parameter HSTROBE_ACTIVE=7'b0000010;
parameter WAITING_DATA=7'b0000100;
parameter HSTROBE_INACTIVE=7'b0001000;
parameter END_CHANGE=7'b0010000;
parameter EMPTY=7'b0100000;
parameter IDLE=7'b1000000;*/
parameter state1=8'b00000001;
parameter state2=8'b00000010;
parameter state3=8'b00000100;
parameter state4=8'b00001000;
parameter state5=8'b00010000;
parameter state6=8'b00100000;
parameter state7=8'b01000000;
parameter state8=8'b10000000;
parameter DPIC=32'h00000000;// control data
parameter DPIA=32'h000D223C;// address data
parameter DPID=32'h05050505;// write or read data
parameter write=1'b0;
parameter read=1'b1;
wire ready;
wire plllocked;
assign ready=hrdy;
assign plllocked=locked;
assign hd=(rw==0)?hd_reg:32'bz;
always @ (posedge sysclk)
begin
if(cnt2<=28'h02dc6c0)
begin
cnt2<=cnt2+1;
dspreset<=0;
end
else
begin
cnt2<=28'h4000011;
dspreset<=1;
end
end
always @ (posedge sysclk)
begin
tdata<=data1;
end
always @ (posedge sysclk )
begin
if(plllocked)//PLL locked go
begin
//dspreset<=1;
case (step)
state1:
begin
rw<=wrcontrol;
hcs<=0;
hds1<=1;
hds2<=1;
step<=state2;
hcntl<=control;
end
state2:
begin
hds2<=0;
step<=state3;
end
state3:
begin
step<=state4;
end
state4:
begin
if(ready==0)
begin
step<=state5;
if(rw==0)
begin
hd_reg<=data;
end
else
begin
//data1<=hd;
end
end
else
begin
step<=state4;
end
end
state5:
begin
hds2<=1;
if(rw==1)
begin
data1<=hd;
end
else
begin
//hd_reg<=data;
end
step<=state6;
end
state6:
begin
if(cnt==3'b000)
begin
hcs<=1;
end
else if(cnt==3'b101)
begin
hcs<=1;
end
else
begin
hcs<=0;
end
step<=state7;
if(cnt==3'b101)
begin
cnt<=3'b000;
end
else
begin
cnt<=cnt+1;
end
end
state7:
begin
step<=state8;
end
state8:
begin
step<=state1;
end
default :
begin
step<=state1;
hcs<=1;
hds1<=1;
hds2<=1;
cnt<=3'b000;
end
endcase
end
else// PLL unlock wait
begin
cnt<=3'b000;
step<=state1;
hcs<=1;
hds1<=1;
hds2<=1;
//dspreset<=0;
end
end
always @ (posedge sysclk)
begin
if(plllocked)
begin
if(cnt>=3'b010)
begin
//wrcontrol<=read;
wrcontrol<=1'b1;
end
else
begin
//wrcontrol<=write;
wrcontrol<=1'b0;
end
end
else
begin
//wrcontrol<=write;
wrcontrol<=1'b0;
end
end
always @ (posedge sysclk)
begin
if(plllocked)
begin
if(cnt==3'b000)
begin
control<=2'b00;//HPIC
data<=32'h00000000;//DPIC
end
else if(cnt==3'b001)
begin
control<=2'b01;//HPIA
data<=32'h000c4844;//DPIA
end
else if(cnt==3'b010)
begin
control<=2'b10;//READ AUTOINCREMENT DPID
end
else if(cnt==3'b011)
begin
control<=2'b10;
end
else if(cnt==3'b100)
begin
control<=2'b10;
end
else if(cnt==3'b101)
begin
control<=2'b11;
end
else
begin
control<=2'b00;//HPIC
data<=32'h00000000;//DPIC
end
end
else
begin
control<=2'b00;//HPIC
data<=32'h00000000;//DPIC
end
end
endmodule
