Tool/software:
This device is not booting properly when configured for parallel flash over EMIF. It is connected to a serial spi flash device through an FPGA which runs at about 12MHz. A single word read takes on the order of 6-15uS depending on first access or sequential. According to my tests through code composer it appears the MEWC field defaults to 0x1C which is about 4.5uS at 100MHz EMIF. The device access at boot needs to be slowed down but the interface itself is fine. Is there any way to default the part to have a slower EMIF clock rate or higher maximum wait cycle time?
