AM62A7: U-boot: Specific clock and device platform data missing cpsw3G support

Job Sava

Part Number: AM62A7
Other Parts Discussed in Thread: SYSCONFIG, AM62P

Tool/software:

Hello,

I am currently working on enabling Ethernet boot on a custom AM62A-based board and have encountered an obstacle. From my understanding, TI does not officially support Ethernet boot for the AM62A.

I have made significant progress toward implementing this functionality; however, I noticed that the arch/arm/mach-k3/r5/am62ax/dev-data.c and arch/arm/mach-k3/r5/am62ax/clk-data.c files do not include an entry for cpsw3g ethernet@8000000 as described in arch/arm/dts/k3-am62a-main.dtsi. As a result, the Ethernet device and clocks are not detected in the SPL, which I suspect is due to it not being registered in dev-data.c and clk-data.c.

According to the file header, dev-data.c and clk-data.c appears to be auto-generated by Bryan Brattlof <bb@ti.com>. Is there a way to include the Ethernet device and clocks in these files so that they can be initialized and used by the SPL?

Thank you for the assistance!

Best Regards,

Job

8 months ago

0 Jonathan Cormier 8 months ago

Genius 4061 points

Job Sava said:
According to the file header, dev-data.c and clk-data.c appears to be auto-generated by Bryan Brattlof <bb@ti.com>. Is there a way to include the Ethernet device and clocks in these files so that they can be initialized and used by the SPL?

Is the tool used to auto generate these files available through the sysconfig clock tree or similar? If not could TI provide us with an updated dev-data.c and clk-data.c file? We are fine with testing and incorporating it into our own branch.

0 Daolin Qiu 7 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hello Jonathan,

Apologies for the delayed response.

Jonathan Cormier said:
Is the tool used to auto generate these files available through the sysconfig clock tree or similar? If not could TI provide us with an updated dev-data.c and clk-data.c file? We are fine with testing and incorporating it into our own branch.

Let me check internally on this. It could be the case that dev-data.c and clk-data.c aren't the files used for cpsw3g in the dtsi and it might be some other files.

What Kernel version/Linux SDK version are you developing on?

-Daolin

0 Jonathan Cormier 7 months ago in reply to Daolin Qiu

Genius 4061 points

Daolin Qiu said:
Let me check internally on this. It could be the case that dev-data.c and clk-data.c aren't the files used for cpsw3g in the dtsi and it might be some other files.

What Kernel version/Linux SDK version are you developing on?

We based our conclusion on how the AM62x and AM62P were setup, both which do support ethernet boot. They have entries in dev-data.c and clk-data.c which correspond with the cpsw. We were able to make some guestimates of what the PSC values were in the 62a dev-data.c file but have no idea how to convert info from the syscfg clock tree tool, into the clk-data.c format.

0 Daolin Qiu 7 months ago

TI__Mastermind 19125 points

Hi Jonathan,

Job Sava said:
I noticed that the arch/arm/mach-k3/r5/am62ax/dev-data.c and arch/arm/mach-k3/r5/am62ax/clk-data.c

I tried looking into where these files are located in the Linux source tree did not find the "mach-k3" directory. Can you point me to where you are finding these files?

Feedback I got internally was that there another tool we use internally to auto-generate the dev-data.c and clk-data.c files but I'm still waiting on some more clarification on whether this tool is something that is available publically.

-Daolin

0 Jonathan Cormier 7 months ago in reply to Daolin Qiu

Genius 4061 points

Daolin Qiu said:
I tried looking into where these files are located in the Linux source tree did not find the "mach-k3" directory. Can you point me to where you are finding these files?

These are in u-boot

Daolin Qiu said:
Feedback I got internally was that there another tool we use internally to auto-generate the dev-data.c and clk-data.c files but I'm still waiting on some more clarification on whether this tool is something that is available publically.

I'm fine with TI running the tool for us and we can test the results.

0 Daolin Qiu 7 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hi Jonathan,

Jonathan Cormier said:
These are in u-boot

Thanks, I had forgotten this is under the context of U-boot not Linux.

Jonathan Cormier said:
I'm fine with TI running the tool for us and we can test the results.

Please try verifying Ethernet boot with the below files

Fullscreen 1588.dev-data.c Download

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x04000000),
	[1] = PSC(1, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
	[1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
	[3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]),
	[2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]),
	[3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
	[10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
	[11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
	[12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
	[13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(95, &soc_lpsc_list[0]),
	PSC_DEV(107, &soc_lpsc_list[0]),
	PSC_DEV(178, &soc_lpsc_list[1]),
	PSC_DEV(179, &soc_lpsc_list[2]),
	PSC_DEV(57, &soc_lpsc_list[3]),
	PSC_DEV(58, &soc_lpsc_list[4]),
	PSC_DEV(161, &soc_lpsc_list[5]),
	PSC_DEV(162, &soc_lpsc_list[6]),
	PSC_DEV(75, &soc_lpsc_list[7]),
	PSC_DEV(102, &soc_lpsc_list[8]),
	PSC_DEV(146, &soc_lpsc_list[8]),
	PSC_DEV(166, &soc_lpsc_list[9]),
	PSC_DEV(135, &soc_lpsc_list[10]),
	PSC_DEV(170, &soc_lpsc_list[11]),
	PSC_DEV(177, &soc_lpsc_list[12]),
	PSC_DEV(55, &soc_lpsc_list[13]),
};

const struct ti_k3_pd_platdata am62ax_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = 2,
	.num_pd = 4,
	.num_lpsc = 14,
	.num_devs = 19,
};

Fullscreen 8030.clk-data.c Download

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_hfosc0_clkout",
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
	"board_0_mmc0_clklb_out",
	"board_0_mmc0_clk_out",
};

static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
	"board_0_mmc1_clklb_out",
	"board_0_mmc1_clk_out",
};

static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
	"board_0_ospi0_dqs_out",
	"board_0_ospi0_lbclko_out",
};

static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const main_usb1_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};

static const char * const wkup_clkout_sel_out0_parents[] = {
	NULL,
	"gluelogic_lfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout2_clk",
	"hsdiv4_16fft_main_1_hsdivout2_clk",
	"postdiv4_16ff_main_2_hsdivout9_clk",
	"clk_32k_rc_sel_out0",
	"gluelogic_rcosc_clkout",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clkout_sel_io_out0_parents[] = {
	"wkup_clkout_sel_out0",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clksel_out0_parents[] = {
	"hsdiv2_16fft_main_15_hsdivout0_clk",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const main_usart0_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out0",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
	DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
	DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(61, 9, "wkup_clksel_out0"),
	DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
	DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
	DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
	DEV_CLK(95, 2, "wkup_clksel_out0"),
	DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(107, 0, "wkup_clksel_out0"),
	DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
	DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
	DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(162, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 2, "board_0_tck_out"),
	DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata am62ax_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = 80,
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = 104,
};

-Daolin

0 Jonathan Cormier 7 months ago in reply to Daolin Qiu

Genius 4061 points

The generated files are a close match to what is already in the u-boot-2024.04 branch, except for updated Copyright, and "PSC_DEV(36" being removed.

diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35e0beb..fa2b23b1fbbd 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08a..fec536898bfe 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -52,7 +52,6 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(161, &soc_lpsc_list[5]),
        PSC_DEV(162, &soc_lpsc_list[6]),
        PSC_DEV(75, &soc_lpsc_list[7]),
-       PSC_DEV(36, &soc_lpsc_list[8]),
        PSC_DEV(102, &soc_lpsc_list[8]),

In dev-data there needs to be a "PSC_DEV(13" entry which corresponds to the cpsw. I think the entry should look something like this based on the AM62x/AM62P dev-data.c files, and a cross check witth the TRM.

diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08a..61ccf1ca1ad2 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -37,6 +37,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
        [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
        [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
        [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
+       [14] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -60,6 +61,7 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(170, &soc_lpsc_list[11]),
        PSC_DEV(177, &soc_lpsc_list[12]),
        PSC_DEV(55, &soc_lpsc_list[13]),
+       PSC_DEV(13, &soc_lpsc_list[14]),
 };

If I diff the AM62x and AM62ax clk-data.c files, I can get a rough idea of which clock entries are missing but I don't really understand what changes are needed to convert from one to the other. The syscfg clock tree tool doesn't seem to give enough info.

u-boot-mitysom-2024.04/arch/arm/mach-k3/r5$ diff -u am62x/clk-data.c am62ax/clk-data.c 
--- am62x/clk-data.c    2025-08-25 15:16:15.642046928 -0400
+++ am62ax/clk-data.c   2025-08-25 15:59:16.935212136 -0400
@@ -1,9 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * AM62X specific clock platform data
+ * AM62AX specific clock platform data
  *
  * This file is auto generated. Please do not hand edit and report any issues
- * to Dave Gerlach <d-gerlach@ti.com>.
+ * to Bryan Brattlof <bb@ti.com>.
  *
  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
@@ -20,6 +20,13 @@
        NULL,
 };
 
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+       "gluelogic_rcosc_clk_1p0v_97p65k",
+       "gluelogic_hfosc0_clkout",
+       "gluelogic_rcosc_clk_1p0v_97p65k",
+       "gluelogic_lfosc0_clkout",
+};
+
 static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
        "board_0_mmc0_clklb_out",
        "board_0_mmc0_clk_out",
@@ -57,25 +64,7 @@
 
 static const char * const clkout0_ctrl_out0_parents[] = {
        "hsdiv4_16fft_main_2_hsdivout1_clk",
-       "hsdiv4_16fft_main_2_hsdivout1_clk10",
-};
-
-static const char * const clk_32k_rc_sel_out0_parents[] = {
-       "gluelogic_rcosc_clk_1p0v_97p65k",
-       "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
-       "clk_32k_rc_sel_div_clkout",
-       "gluelogic_lfosc0_clkout",
-};
-
-static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
-       "postdiv4_16ff_main_2_hsdivout5_clk",
-       "postdiv4_16ff_main_0_hsdivout6_clk",
-       "board_0_cp_gemac_cpts0_rft_clk_out",
-       NULL,
-       "board_0_mcu_ext_refclk0_out",
-       "board_0_ext_refclk1_out",
-       "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
-       "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+       "hsdiv4_16fft_main_2_hsdivout1_clk",
 };
 
 static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
@@ -105,7 +94,7 @@
 };
 
 static const char * const wkup_clkout_sel_out0_parents[] = {
-       "gluelogic_hfosc0_clkout",
+       NULL,
        "gluelogic_lfosc0_clkout",
        "hsdiv4_16fft_main_0_hsdivout2_clk",
        "hsdiv4_16fft_main_1_hsdivout2_clk",
@@ -115,8 +104,13 @@
        "gluelogic_hfosc0_clkout",
 };
 
+static const char * const wkup_clkout_sel_io_out0_parents[] = {
+       "wkup_clkout_sel_out0",
+       "gluelogic_hfosc0_clkout",
+};
+
 static const char * const wkup_clksel_out0_parents[] = {
-       "hsdiv1_16fft_main_15_hsdivout0_clk",
+       "hsdiv2_16fft_main_15_hsdivout0_clk",
        "hsdiv4_16fft_mcu_0_hsdivout0_clk",
 };
 
@@ -143,20 +137,10 @@
        CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
        CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
        CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
        CLK_FIXED_RATE("board_0_tck_out", 0, 0),
-       CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
-       CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
-       CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
        CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
        CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
        CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
-       CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
        CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
        CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
        CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
@@ -178,6 +162,7 @@
        CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
        CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
        CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
+       CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
        CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
        CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
        CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
@@ -185,7 +170,7 @@
        CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
        CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
        CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
-       CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
+       CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
@@ -195,7 +180,6 @@
        CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
-       CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
        CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -203,14 +187,13 @@
        CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
        CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
        CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
-       CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
-       CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
        CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
        CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
        CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
        CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
        CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
        CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
+       CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
        CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
        CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
@@ -220,29 +203,6 @@
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
-       DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-       DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
-       DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
-       DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
-       DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
-       DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
-       DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
-       DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
-       DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-       DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
-       DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
-       DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
-       DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
-       DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
-       DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
        DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
        DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
        DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -279,7 +239,7 @@
        DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(61, 9, "wkup_clksel_out0"),
-       DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+       DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"),
        DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
        DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
        DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -294,18 +254,16 @@
        DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
        DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
        DEV_CLK(95, 2, "wkup_clksel_out0"),
-       DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+       DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"),
        DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
        DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
        DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
        DEV_CLK(107, 0, "wkup_clksel_out0"),
-       DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+       DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"),
        DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
-       DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
        DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
        DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
-       DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
        DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
@@ -314,28 +272,20 @@
        DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 20, "clkout0_ctrl_out0"),
        DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
+       DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
        DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
        DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
        DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
-       DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
        DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
+       DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
        DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
        DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
-       DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
-       DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
-       DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
-       DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
-       DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
-       DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
-       DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
-       DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
-       DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
-       DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
-       DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
-       DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
-       DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
+       DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+       DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
+       DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
+       DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
+       DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"),
        DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -354,14 +304,14 @@
        DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-       DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
-       DEV_CLK(170, 1, "board_0_tck_out"),
-       DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+       DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+       DEV_CLK(170, 2, "board_0_tck_out"),
+       DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 };
 
-const struct ti_k3_clk_platdata am62x_clk_platdata = {
+const struct ti_k3_clk_platdata am62ax_clk_platdata = {
        .clk_list = clk_list,
-       .clk_list_cnt = 90,
+       .clk_list_cnt = 80,
        .soc_dev_clk_data = soc_dev_clk_data,
-       .soc_dev_clk_data_cnt = 137,
+       .soc_dev_clk_data_cnt = 104,
 };

0 Jonathan Cormier 7 months ago in reply to Jonathan Cormier

Genius 4061 points

Jonathan Cormier said:
The generated files are a close match to what is already in the u-boot-2024.04 branch, except for updated Copyright, and "PSC_DEV(36" being removed.

Looks like I didn't say it specifically but the provided files didn't help.

0 Daolin Qiu 7 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hi Jonathan,

Apologies for the delayed response again, I was/am out of office this week.

I just noticed the files I shared with you (which were provided to me by our software team) appears to be the same as those from https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/mach-k3/r5/am62ax/?h=ti-u-boot-2024.10 (as you mentioned).

Job Sava said:
As a result, the Ethernet device and clocks are not detected in the SPL, which I suspect is due to it not being registered in dev-data.c and clk-data.c.

Can you please provide the exact log showing the error/issue?

-Daolin

0 Jonathan Cormier 6 months ago in reply to Daolin Qiu

Genius 4061 points

Sorry I don't have access to those logs but they were complaining about missing the PSC_DEV(13 node

0 Daolin Qiu 6 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hi Jonathan,

I learned that the developer had used the below versions of clk-data.c and dev-data.c and while working with AM62A Ethernet boot on AM62A TI EVM. I also did a quick diff and there are several differences between this version and the version of the files I shared before. It might be a good starting point for enabling Ethernet boot on AM62A on your custom board.

clk-data.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_hfosc0_clkout",
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
	"board_0_mmc0_clklb_out",
	"board_0_mmc0_clk_out",
};
static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const main_usb1_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};
};

static const char * const main_usart0_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out0",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
	DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
	DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
	DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
	DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
	DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
	DEV_CLK(95, 2, "wkup_clksel_out0"),
	DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(107, 0, "wkup_clksel_out0"),
	DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 133, "cpsw_3guss_main_0_rgmii1_txc_o"),
	DEV_CLK(157, 136, "cpsw_3guss_main_0_rgmii2_txc_o"),
	DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
	DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
	DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(162, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 2, "board_0_tck_out"),
	DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata am62ax_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = 80,
	.clk_list_cnt = 90,
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = 104,
	.soc_dev_clk_data_cnt = 130,
};

dev-data.c

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 * Copyright (C) 2020-2023 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x04000000),
	[1] = PSC(1, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
	[1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
	[3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
	[1] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[3] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[2]),
	[4] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]),
	[2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]),
	[3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
	[10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
	[11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
	[12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
	[13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
	[9] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
	[10] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[8]),
	[11] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[10]),
	[12] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[8]),
	[13] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[12]),
	[14] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[13]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(95, &soc_lpsc_list[0]),
	PSC_DEV(107, &soc_lpsc_list[0]),
	PSC_DEV(178, &soc_lpsc_list[1]),
	PSC_DEV(179, &soc_lpsc_list[2]),
	PSC_DEV(57, &soc_lpsc_list[3]),
	PSC_DEV(58, &soc_lpsc_list[4]),
	PSC_DEV(161, &soc_lpsc_list[5]),
	PSC_DEV(162, &soc_lpsc_list[6]),
	PSC_DEV(75, &soc_lpsc_list[7]),
	PSC_DEV(102, &soc_lpsc_list[8]),
	PSC_DEV(146, &soc_lpsc_list[8]),
	PSC_DEV(166, &soc_lpsc_list[9]),
	PSC_DEV(135, &soc_lpsc_list[10]),
	PSC_DEV(170, &soc_lpsc_list[11]),
	PSC_DEV(177, &soc_lpsc_list[12]),
	PSC_DEV(55, &soc_lpsc_list[13]),
	PSC_DEV(13, &soc_lpsc_list[9]),
	PSC_DEV(166, &soc_lpsc_list[10]),
	PSC_DEV(135, &soc_lpsc_list[11]),
	PSC_DEV(170, &soc_lpsc_list[12]),
	PSC_DEV(177, &soc_lpsc_list[13]),
	PSC_DEV(55, &soc_lpsc_list[14]),
};

const struct ti_k3_pd_platdata am62ax_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = 2,
	.num_pd = 4,
	.num_lpsc = 14,
	.num_devs = 19,
	.num_pd = 5,
	.num_lpsc = 15,
	.num_devs = 20,
};

Let us know if you have additional questions. It would be helpful if you are able to get access to the logs and share if you are still facing issues with this.

-Daolin

0 Jonathan Cormier 6 months ago in reply to Daolin Qiu

Genius 4061 points

Thanks sorry for the slow response, I've had several fires pop up. Will get back to this

0 Daolin Qiu 6 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

No problem, let me know if you have additional questions.

-Daolin

0 Jonathan Cormier 6 months ago in reply to Daolin Qiu

Genius 4061 points

I think I've made some further progress. However now the ti_sci message seems to be failing, though I'm not sure why or how to dig into it.

[15:17:49.747] U-Boot SPL 2025.01-00631-gf6c5a371dab2-dirty (Oct 10 2025 - 15:17:21 -0400)
[15:17:49.747] SYSFW ABI: 4.0 (firmware rev 0x000b '11.1.5--v11.01.05 (Fancy Rat)')
[15:17:49.949] Configuring LPDDR4 for 4GB
[15:17:50.061] SPL initial stack usage: 13568 bytes
[15:17:50.084] Trying to boot from eth device
[15:17:50.084] Loading Environment from nowhere... OK
...
[15:17:50.324] uclass_get_device_tail: probing mailbox@4d000000 returned 0
[15:17:50.325] uclass_get_device_tail: probing mailbox@4d000000 returned 0
[15:17:50.325] uclass_get_device_tail: probing dm-tifs returned 0
[15:17:50.348] uclass_get_device_tail: probing dma-controller@485c0000 returned 0
[15:17:50.348] ti_sci_dm dm-tifs: RM_PSIL: nav: 25 link pair 4115->50688
[15:17:50.348] ti_sci_dm dm-tifs: Message not acknowledged
[15:17:50.348] ti-udma dma-controller@485c0000: PSI-L pairing failed: 0x1013 -> 0xc600
[15:17:50.349] ti-udma dma-controller@485c0000: alloc dma res failed -19
[15:17:50.370] am65_cpsw_nuss_port ethernet@8000000port@1: TX dma get failed -22
[15:17:50.370] am65_cpsw_nuss_port ethernet@8000000port@1: am65_cpsw_start end error
...
[15:18:17.105] BOOTP broadcast 17

[15:18:19.039] Retry time exceeded; starting again
[15:18:19.039] Problem booting with BOOTP
[15:18:19.039] SPL: failed to boot from all boot devices
[15:18:19.039] ### ERROR ### Please RESET the board ###

0 Daolin Qiu 6 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hi Jonathan,

Are you currently using the same clk-data.c and dev-data.c I shared or have you made modifications to it?

-Daolin

0 Jonathan Cormier 6 months ago in reply to Daolin Qiu

Genius 4061 points

I had to merge it into my copy of the files. Your copy had duplicate array numbers and changed some of the existing values which would have broken other clk entries which I didn't want to get into.

If I made a mistake would that cause a link pair error?

Fullscreen 1121.clk-data.c Download

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_hfosc0_clkout",
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
	"board_0_mmc0_clklb_out",
	"board_0_mmc0_clk_out",
};

static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
	"board_0_mmc1_clklb_out",
	"board_0_mmc1_clk_out",
};

static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
	"board_0_ospi0_dqs_out",
	"board_0_ospi0_lbclko_out",
};

static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const main_usb1_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};

static const char * const wkup_clkout_sel_out0_parents[] = {
	NULL,
	"gluelogic_lfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout2_clk",
	"hsdiv4_16fft_main_1_hsdivout2_clk",
	"postdiv4_16ff_main_2_hsdivout9_clk",
	"clk_32k_rc_sel_out0",
	"gluelogic_rcosc_clkout",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clkout_sel_io_out0_parents[] = {
	"wkup_clkout_sel_out0",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clksel_out0_parents[] = {
	"hsdiv2_16fft_main_15_hsdivout0_clk",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const main_usart0_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out0",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
	CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
	DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
	DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
	DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
	DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
	DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
	DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
	DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
	DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(61, 9, "wkup_clksel_out0"),
	DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
	DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
	DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
	DEV_CLK(95, 2, "wkup_clksel_out0"),
	DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(107, 0, "wkup_clksel_out0"),
	DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 133, "cpsw_3guss_main_0_rgmii1_txc_o"),
	DEV_CLK(157, 136, "cpsw_3guss_main_0_rgmii2_txc_o"),
	DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
	DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
	DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(162, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 2, "board_0_tck_out"),
	DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata am62ax_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = ARRAY_SIZE(clk_list),
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = ARRAY_SIZE(soc_dev_clk_data),
};

Fullscreen 1121.dev-data.c Download

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x04000000),
	[1] = PSC(1, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
	[1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
	[3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
	[4] = PSC_PD(2, &soc_psc_list[1], &soc_pd_list[0]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]),
	[2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]),
	[3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
	[10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
	[11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
	[12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
	[13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
	[14] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[4], &soc_lpsc_list[8]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(95, &soc_lpsc_list[0]),
	PSC_DEV(107, &soc_lpsc_list[0]),
	PSC_DEV(178, &soc_lpsc_list[1]),
	PSC_DEV(179, &soc_lpsc_list[2]),
	PSC_DEV(57, &soc_lpsc_list[3]),
	PSC_DEV(58, &soc_lpsc_list[4]),
	PSC_DEV(161, &soc_lpsc_list[5]),
	PSC_DEV(162, &soc_lpsc_list[6]),
	PSC_DEV(75, &soc_lpsc_list[7]),
	PSC_DEV(36, &soc_lpsc_list[8]),
	PSC_DEV(102, &soc_lpsc_list[8]),
	PSC_DEV(146, &soc_lpsc_list[8]),
	PSC_DEV(166, &soc_lpsc_list[9]),
	PSC_DEV(135, &soc_lpsc_list[10]),
	PSC_DEV(170, &soc_lpsc_list[11]),
	PSC_DEV(177, &soc_lpsc_list[12]),
	PSC_DEV(55, &soc_lpsc_list[13]),
	PSC_DEV(13, &soc_lpsc_list[14]),
};

const struct ti_k3_pd_platdata am62ax_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = ARRAY_SIZE(soc_psc_list),
	.num_pd = ARRAY_SIZE(soc_pd_list),
	.num_lpsc = ARRAY_SIZE(soc_lpsc_list),
	.num_devs = ARRAY_SIZE(soc_dev_list),
};

0 Daolin Qiu 6 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hi Jonathan,

Apologies for the delay in response. I recently learned that our software team has plans to enable Ethernet boot for AM62A out of box and, depending on how long it takes to implement, it may be implemented into the next SDK release (still subject to change).

Unfortunately, because the issue you are facing is due to many specific custom changes you implemented on top of the out of box SDK, it will take significant amount of time and resources to completely replicate exactly the changes you made and debug the issue. If it is an issue from the unmodified SDK then we will be able to help but if it's an issue from making custom changes to the SDK, then our support is limited.

Since we have plans to enable Ethernet boot for AM62A out of box for the next SDK release (planned for Nov/Dec but subject to change), it might be better to use the feature when it has been enabled out of box.

Please let me know if you have additional concerns.

-Daolin

0 Jonathan Cormier 6 months ago in reply to Daolin Qiu

Genius 4061 points

Daolin Qiu said:
Unfortunately, because the issue you are facing is due to many specific custom changes you implemented on top of the out of box SDK

How do you figure? The code you provided didn't cleanly fit into the u-boot 2025 branch version of the files and your message implied it was random changes laying around, so I felt i needed to merge the changes in. This is not "specific custom changes".

I am happy to test this on the TI 62A evm if that makes it easier on you. But there isn't a lot of difference between that board and ours.

Daolin Qiu said:
Since we have plans to enable Ethernet boot for AM62A out of box for the next SDK release (planned for Nov/Dec but subject to change), it might be better to use the feature when it has been enabled out of box.

Glad to hear there is an upcoming release. I'd be happy to help them test changes so we can improve the changes of it getting into the next release.

0 Daolin Qiu 5 months ago in reply to Jonathan Cormier

TI__Mastermind 19125 points

Hi Jonathan,

Jonathan Cormier said:
I am happy to test this on the TI 62A evm if that makes it easier on you. But there isn't a lot of difference between that board and ours.

It's great that you are willing to test but the problem is that we need to be able to replicate the issue as well to be able to have an idea on what to suggest to fix the issue. It isn't specifically custom changes but the fact that we currently don't support Ethernet boot out of box for AM62A so any changes to enable it would also count as changing the out of box SDK.

Jonathan Cormier said:
Glad to hear there is an upcoming release. I'd be happy to help them test changes so we can improve the changes of it getting into the next release.

I will let the software developer know in case having an additional person to test out the changes can help with the feature release.

-Daolin

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