AM62A7: U-boot: Specific clock and device platform data missing cpsw3G support

Job Sava said:

According to the file header, dev-data.c and clk-data.c appears to be auto-generated by Bryan Brattlof <bb@ti.com>. Is there a way to include the Ethernet device and clocks in these files so that they can be initialized and used by the SPL?

Is the tool used to auto generate these files available through the sysconfig clock tree or similar?  If not could TI provide us with an updated dev-data.c and clk-data.c file? We are fine with testing and incorporating it into our own branch.

Hello Jonathan,

Apologies for the delayed response.

Jonathan Cormier said:

Is the tool used to auto generate these files available through the sysconfig clock tree or similar?  If not could TI provide us with an updated dev-data.c and clk-data.c file? We are fine with testing and incorporating it into our own branch.

Let me check internally on this. It could be the case that dev-data.c and clk-data.c aren't the files used for cpsw3g in the dtsi and it might be some other files. 

What Kernel version/Linux SDK version are you developing on?

-Daolin

Daolin Qiu said:

Let me check internally on this. It could be the case that dev-data.c and clk-data.c aren't the files used for cpsw3g in the dtsi and it might be some other files. 

What Kernel version/Linux SDK version are you developing on?

We based our conclusion on how the AM62x and AM62P were setup, both which do support ethernet boot.  They have entries in dev-data.c and clk-data.c which correspond with the cpsw.  We were able to make some guestimates of what the PSC values were in the 62a dev-data.c file but have no idea how to convert info from the syscfg clock tree tool, into the clk-data.c format.

Hi Jonathan,

Job Sava said:

I noticed that the arch/arm/mach-k3/r5/am62ax/dev-data.c and arch/arm/mach-k3/r5/am62ax/clk-data.c

I tried looking into where these files are located in the Linux source tree did not find the "mach-k3" directory. Can you point me to where you are finding these files?

Feedback I got internally was that there another tool we use internally to auto-generate the dev-data.c and clk-data.c files but I'm still waiting on some more clarification on whether this tool is something that is available publically.

-Daolin

Daolin Qiu said:

I tried looking into where these files are located in the Linux source tree did not find the "mach-k3" directory. Can you point me to where you are finding these files?

These are in u-boot

Daolin Qiu said:

Feedback I got internally was that there another tool we use internally to auto-generate the dev-data.c and clk-data.c files but I'm still waiting on some more clarification on whether this tool is something that is available publically.

I'm fine with TI running the tool for us and we can test the results.

Hi Jonathan, 

Jonathan Cormier said:

These are in u-boot

Thanks, I had forgotten this is under the context of U-boot not Linux. 

Jonathan Cormier said:

I'm fine with TI running the tool for us and we can test the results.

Please try verifying Ethernet boot with the below files

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific device platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

#include "k3-dev.h"

static struct ti_psc soc_psc_list[] = {
	[0] = PSC(0, 0x04000000),
	[1] = PSC(1, 0x00400000),
};

static struct ti_pd soc_pd_list[] = {
	[0] = PSC_PD(0, &soc_psc_list[1], NULL),
	[1] = PSC_PD(3, &soc_psc_list[1], &soc_pd_list[0]),
	[2] = PSC_PD(4, &soc_psc_list[1], &soc_pd_list[1]),
	[3] = PSC_PD(13, &soc_psc_list[1], &soc_pd_list[0]),
};

static struct ti_lpsc soc_lpsc_list[] = {
	[0] = PSC_LPSC(0, &soc_psc_list[1], &soc_pd_list[0], NULL),
	[1] = PSC_LPSC(12, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[5]),
	[2] = PSC_LPSC(13, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[6]),
	[3] = PSC_LPSC(20, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[4] = PSC_LPSC(21, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[5] = PSC_LPSC(23, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[6] = PSC_LPSC(24, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[7] = PSC_LPSC(28, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[8] = PSC_LPSC(34, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
	[9] = PSC_LPSC(43, &soc_psc_list[1], &soc_pd_list[1], &soc_lpsc_list[8]),
	[10] = PSC_LPSC(46, &soc_psc_list[1], &soc_pd_list[2], &soc_lpsc_list[9]),
	[11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
	[12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
	[13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
};

static struct ti_dev soc_dev_list[] = {
	PSC_DEV(16, &soc_lpsc_list[0]),
	PSC_DEV(77, &soc_lpsc_list[0]),
	PSC_DEV(61, &soc_lpsc_list[0]),
	PSC_DEV(95, &soc_lpsc_list[0]),
	PSC_DEV(107, &soc_lpsc_list[0]),
	PSC_DEV(178, &soc_lpsc_list[1]),
	PSC_DEV(179, &soc_lpsc_list[2]),
	PSC_DEV(57, &soc_lpsc_list[3]),
	PSC_DEV(58, &soc_lpsc_list[4]),
	PSC_DEV(161, &soc_lpsc_list[5]),
	PSC_DEV(162, &soc_lpsc_list[6]),
	PSC_DEV(75, &soc_lpsc_list[7]),
	PSC_DEV(102, &soc_lpsc_list[8]),
	PSC_DEV(146, &soc_lpsc_list[8]),
	PSC_DEV(166, &soc_lpsc_list[9]),
	PSC_DEV(135, &soc_lpsc_list[10]),
	PSC_DEV(170, &soc_lpsc_list[11]),
	PSC_DEV(177, &soc_lpsc_list[12]),
	PSC_DEV(55, &soc_lpsc_list[13]),
};

const struct ti_k3_pd_platdata am62ax_pd_platdata = {
	.psc = soc_psc_list,
	.pd = soc_pd_list,
	.lpsc = soc_lpsc_list,
	.devs = soc_dev_list,
	.num_psc = 2,
	.num_pd = 4,
	.num_lpsc = 14,
	.num_devs = 19,
};

// SPDX-License-Identifier: GPL-2.0+
/*
 * AM62AX specific clock platform data
 *
 * This file is auto generated. Please do not hand edit and report any issues
 * to Bryan Brattlof <bb@ti.com>.
 *
 * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
 */

#include <linux/clk-provider.h>
#include "k3-clk.h"

static const char * const gluelogic_hfosc0_clkout_parents[] = {
	NULL,
	NULL,
	"osc_24_mhz",
	"osc_25_mhz",
	"osc_26_mhz",
	NULL,
};

static const char * const clk_32k_rc_sel_out0_parents[] = {
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_hfosc0_clkout",
	"gluelogic_rcosc_clk_1p0v_97p65k",
	"gluelogic_lfosc0_clkout",
};

static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
	"board_0_mmc0_clklb_out",
	"board_0_mmc0_clk_out",
};

static const char * const main_emmcsd1_io_clklb_sel_out0_parents[] = {
	"board_0_mmc1_clklb_out",
	"board_0_mmc1_clk_out",
};

static const char * const main_ospi_loopback_clk_sel_out0_parents[] = {
	"board_0_ospi0_dqs_out",
	"board_0_ospi0_lbclko_out",
};

static const char * const main_usb0_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const main_usb1_refclk_sel_out0_parents[] = {
	"gluelogic_hfosc0_clkout",
	"postdiv4_16ff_main_0_hsdivout8_clk",
};

static const char * const sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout0_clk",
};

static const char * const sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents[] = {
	"gluelogic_hfosc0_clkout",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const clkout0_ctrl_out0_parents[] = {
	"hsdiv4_16fft_main_2_hsdivout1_clk",
	"hsdiv4_16fft_main_2_hsdivout1_clk",
};

static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_emmcsd1_refclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_0_hsdivout5_clk",
	"hsdiv4_16fft_main_2_hsdivout2_clk",
};

static const char * const main_gtcclk_sel_out0_parents[] = {
	"postdiv4_16ff_main_2_hsdivout5_clk",
	"postdiv4_16ff_main_0_hsdivout6_clk",
	"board_0_cp_gemac_cpts0_rft_clk_out",
	NULL,
	"board_0_mcu_ext_refclk0_out",
	"board_0_ext_refclk1_out",
	"sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
	"sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
};

static const char * const main_ospi_ref_clk_sel_out0_parents[] = {
	"hsdiv4_16fft_main_0_hsdivout1_clk",
	"postdiv1_16fft_main_1_hsdivout5_clk",
};

static const char * const wkup_clkout_sel_out0_parents[] = {
	NULL,
	"gluelogic_lfosc0_clkout",
	"hsdiv4_16fft_main_0_hsdivout2_clk",
	"hsdiv4_16fft_main_1_hsdivout2_clk",
	"postdiv4_16ff_main_2_hsdivout9_clk",
	"clk_32k_rc_sel_out0",
	"gluelogic_rcosc_clkout",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clkout_sel_io_out0_parents[] = {
	"wkup_clkout_sel_out0",
	"gluelogic_hfosc0_clkout",
};

static const char * const wkup_clksel_out0_parents[] = {
	"hsdiv2_16fft_main_15_hsdivout0_clk",
	"hsdiv4_16fft_mcu_0_hsdivout0_clk",
};

static const char * const main_usart0_fclk_sel_out0_parents[] = {
	"usart_programmable_clock_divider_out0",
	"hsdiv4_16fft_main_1_hsdivout1_clk",
};

static const struct clk_data clk_list[] = {
	CLK_FIXED_RATE("osc_26_mhz", 26000000, 0),
	CLK_FIXED_RATE("osc_25_mhz", 25000000, 0),
	CLK_FIXED_RATE("osc_24_mhz", 24000000, 0),
	CLK_MUX("gluelogic_hfosc0_clkout", gluelogic_hfosc0_clkout_parents, 6, 0x43000030, 0, 3, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clkout", 12500000, 0),
	CLK_FIXED_RATE("gluelogic_rcosc_clk_1p0v_97p65k", 97656, 0),
	CLK_FIXED_RATE("board_0_cp_gemac_cpts0_rft_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ddr0_ck0_out", 0, 0),
	CLK_FIXED_RATE("board_0_ext_refclk1_out", 0, 0),
	CLK_FIXED_RATE("board_0_i2c0_scl_out", 0, 0),
	CLK_FIXED_RATE("board_0_mcu_ext_refclk0_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc0_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clklb_out", 0, 0),
	CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
	CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
	CLK_FIXED_RATE("board_0_tck_out", 0, 0),
	CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
	CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
	CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", 0x680038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_1_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x681000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk_subdiv", 0x681038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_12_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68c000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_15_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x68f000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_main_2_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x682000, 0),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_DIV("pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk_subdiv", 0x682038, 24, 3, 0, CLK_DIVIDER_ONE_BASED),
	CLK_PLL("pllfracf_ssmod_16fft_main_8_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x688000, 0),
	CLK_PLL("pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x4040000, 0),
	CLK_DIV("postdiv1_16fft_main_1_hsdivout5_clk", "pllfracf_ssmod_16fft_main_1_foutpostdiv_clk", 0x681094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout5_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout6_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x680098, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_0_hsdivout8_clk", "pllfracf_ssmod_16fft_main_0_foutpostdiv_clk", 0x6800a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
	CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
	CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
	CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
	CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
	CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
	CLK_MUX("main_usb0_refclk_sel_out0", main_usb0_refclk_sel_out0_parents, 2, 0x43008190, 0, 1, 0),
	CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
	CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
	CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
	CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout3_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x68008c, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_0_hsdivout4_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680090, 0, 7, 0, 0),
	CLK_DIV_DEFFREQ("hsdiv4_16fft_main_1_hsdivout0_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681080, 0, 7, 0, 0, 192000000),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x410118, 0, 5, 0, 0),
	CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
	CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
	CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
	CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
	CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
	CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
	CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
	CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
	CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
	CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
	CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
	CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
	CLK_FIXED_RATE("mshsi2c_wkup_0_porscl", 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_main_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_main_0_sysclkout_clk", 0x41011c, 0, 5, 0, 0),
	CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div24_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x402011c, 0, 5, 0, 0),
};

static const struct dev_clk soc_dev_clk_data[] = {
	DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
	DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
	DEV_CLK(16, 3, "hsdiv4_16fft_main_0_hsdivout4_clk"),
	DEV_CLK(16, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 5, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 7, "postdiv4_16ff_main_2_hsdivout8_clk"),
	DEV_CLK(16, 8, "gluelogic_hfosc0_clkout"),
	DEV_CLK(16, 9, "board_0_ext_refclk1_out"),
	DEV_CLK(16, 10, "gluelogic_rcosc_clkout"),
	DEV_CLK(16, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(16, 12, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 0, "main_emmcsd0_io_clklb_sel_out0"),
	DEV_CLK(57, 1, "board_0_mmc0_clklb_out"),
	DEV_CLK(57, 2, "board_0_mmc0_clk_out"),
	DEV_CLK(57, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(57, 6, "main_emmcsd0_refclk_sel_out0"),
	DEV_CLK(57, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(57, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(58, 0, "main_emmcsd1_io_clklb_sel_out0"),
	DEV_CLK(58, 1, "board_0_mmc1_clklb_out"),
	DEV_CLK(58, 2, "board_0_mmc1_clk_out"),
	DEV_CLK(58, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(58, 6, "main_emmcsd1_refclk_sel_out0"),
	DEV_CLK(58, 7, "postdiv4_16ff_main_0_hsdivout5_clk"),
	DEV_CLK(58, 8, "hsdiv4_16fft_main_2_hsdivout2_clk"),
	DEV_CLK(61, 0, "main_gtcclk_sel_out0"),
	DEV_CLK(61, 1, "postdiv4_16ff_main_2_hsdivout5_clk"),
	DEV_CLK(61, 2, "postdiv4_16ff_main_0_hsdivout6_clk"),
	DEV_CLK(61, 3, "board_0_cp_gemac_cpts0_rft_clk_out"),
	DEV_CLK(61, 5, "board_0_mcu_ext_refclk0_out"),
	DEV_CLK(61, 6, "board_0_ext_refclk1_out"),
	DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(61, 9, "wkup_clksel_out0"),
	DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 2, "main_ospi_loopback_clk_sel_out0"),
	DEV_CLK(75, 3, "board_0_ospi0_dqs_out"),
	DEV_CLK(75, 4, "board_0_ospi0_lbclko_out"),
	DEV_CLK(75, 6, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(75, 7, "main_ospi_ref_clk_sel_out0"),
	DEV_CLK(75, 8, "hsdiv4_16fft_main_0_hsdivout1_clk"),
	DEV_CLK(75, 9, "postdiv1_16fft_main_1_hsdivout5_clk"),
	DEV_CLK(77, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
	DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
	DEV_CLK(95, 2, "wkup_clksel_out0"),
	DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
	DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
	DEV_CLK(107, 0, "wkup_clksel_out0"),
	DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"),
	DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
	DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
	DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
	DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
	DEV_CLK(146, 1, "usart_programmable_clock_divider_out0"),
	DEV_CLK(146, 2, "hsdiv4_16fft_main_1_hsdivout1_clk"),
	DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 20, "clkout0_ctrl_out0"),
	DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
	DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
	DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
	DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
	DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
	DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
	DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
	DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
	DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
	DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(161, 3, "main_usb0_refclk_sel_out0"),
	DEV_CLK(161, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(161, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(161, 10, "board_0_tck_out"),
	DEV_CLK(162, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(162, 3, "main_usb1_refclk_sel_out0"),
	DEV_CLK(162, 4, "gluelogic_hfosc0_clkout"),
	DEV_CLK(162, 5, "postdiv4_16ff_main_0_hsdivout8_clk"),
	DEV_CLK(162, 10, "board_0_tck_out"),
	DEV_CLK(166, 3, "hsdiv0_16fft_main_8_hsdivout0_clk"),
	DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
	DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
	DEV_CLK(170, 2, "board_0_tck_out"),
	DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
};

const struct ti_k3_clk_platdata am62ax_clk_platdata = {
	.clk_list = clk_list,
	.clk_list_cnt = 80,
	.soc_dev_clk_data = soc_dev_clk_data,
	.soc_dev_clk_data_cnt = 104,
};

-Daolin

The generated files are a close match to what is already in the u-boot-2024.04 branch, except for updated Copyright, and "PSC_DEV(36" being removed.

diff --git a/arch/arm/mach-k3/r5/am62ax/clk-data.c b/arch/arm/mach-k3/r5/am62ax/clk-data.c
index d950b35e0beb..fa2b23b1fbbd 100644
--- a/arch/arm/mach-k3/r5/am62ax/clk-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/clk-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include <linux/clk-provider.h>
diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08a..fec536898bfe 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -5,7 +5,7 @@
  * This file is auto generated. Please do not hand edit and report any issues
  * to Bryan Brattlof <bb@ti.com>.
  *
- * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2025 Texas Instruments Incorporated - https://www.ti.com/
  */
 
 #include "k3-dev.h"
@@ -52,7 +52,6 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(161, &soc_lpsc_list[5]),
        PSC_DEV(162, &soc_lpsc_list[6]),
        PSC_DEV(75, &soc_lpsc_list[7]),
-       PSC_DEV(36, &soc_lpsc_list[8]),
        PSC_DEV(102, &soc_lpsc_list[8]),

In dev-data there needs to be a "PSC_DEV(13" entry which corresponds to the cpsw.  I think the entry should look something like this based on the AM62x/AM62P dev-data.c files, and a cross check witth the TRM.

diff --git a/arch/arm/mach-k3/r5/am62ax/dev-data.c b/arch/arm/mach-k3/r5/am62ax/dev-data.c
index 6cced9efd08a..61ccf1ca1ad2 100644
--- a/arch/arm/mach-k3/r5/am62ax/dev-data.c
+++ b/arch/arm/mach-k3/r5/am62ax/dev-data.c
@@ -37,6 +37,7 @@ static struct ti_lpsc soc_lpsc_list[] = {
        [11] = PSC_LPSC(60, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[8]),
        [12] = PSC_LPSC(61, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[11]),
        [13] = PSC_LPSC(62, &soc_psc_list[1], &soc_pd_list[3], &soc_lpsc_list[12]),
+       [14] = PSC_LPSC(42, &soc_psc_list[1], &soc_pd_list[0], &soc_lpsc_list[8]),
 };
 
 static struct ti_dev soc_dev_list[] = {
@@ -60,6 +61,7 @@ static struct ti_dev soc_dev_list[] = {
        PSC_DEV(170, &soc_lpsc_list[11]),
        PSC_DEV(177, &soc_lpsc_list[12]),
        PSC_DEV(55, &soc_lpsc_list[13]),
+       PSC_DEV(13, &soc_lpsc_list[14]),
 };

If I diff the AM62x and AM62ax clk-data.c files, I can get a rough idea of which clock entries are missing but I don't really understand what changes are needed to convert from one to the other.  The syscfg clock tree tool doesn't seem to give enough info.

u-boot-mitysom-2024.04/arch/arm/mach-k3/r5$ diff -u am62x/clk-data.c am62ax/clk-data.c 
--- am62x/clk-data.c    2025-08-25 15:16:15.642046928 -0400
+++ am62ax/clk-data.c   2025-08-25 15:59:16.935212136 -0400
@@ -1,9 +1,9 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * AM62X specific clock platform data
+ * AM62AX specific clock platform data
  *
  * This file is auto generated. Please do not hand edit and report any issues
- * to Dave Gerlach <d-gerlach@ti.com>.
+ * to Bryan Brattlof <bb@ti.com>.
  *
  * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
  */
@@ -20,6 +20,13 @@
        NULL,
 };
 
+static const char * const clk_32k_rc_sel_out0_parents[] = {
+       "gluelogic_rcosc_clk_1p0v_97p65k",
+       "gluelogic_hfosc0_clkout",
+       "gluelogic_rcosc_clk_1p0v_97p65k",
+       "gluelogic_lfosc0_clkout",
+};
+
 static const char * const main_emmcsd0_io_clklb_sel_out0_parents[] = {
        "board_0_mmc0_clklb_out",
        "board_0_mmc0_clk_out",
@@ -57,25 +64,7 @@
 
 static const char * const clkout0_ctrl_out0_parents[] = {
        "hsdiv4_16fft_main_2_hsdivout1_clk",
-       "hsdiv4_16fft_main_2_hsdivout1_clk10",
-};
-
-static const char * const clk_32k_rc_sel_out0_parents[] = {
-       "gluelogic_rcosc_clk_1p0v_97p65k",
-       "hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk",
-       "clk_32k_rc_sel_div_clkout",
-       "gluelogic_lfosc0_clkout",
-};
-
-static const char * const main_cp_gemac_cpts_clk_sel_out0_parents[] = {
-       "postdiv4_16ff_main_2_hsdivout5_clk",
-       "postdiv4_16ff_main_0_hsdivout6_clk",
-       "board_0_cp_gemac_cpts0_rft_clk_out",
-       NULL,
-       "board_0_mcu_ext_refclk0_out",
-       "board_0_ext_refclk1_out",
-       "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk",
-       "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk",
+       "hsdiv4_16fft_main_2_hsdivout1_clk",
 };
 
 static const char * const main_emmcsd0_refclk_sel_out0_parents[] = {
@@ -105,7 +94,7 @@
 };
 
 static const char * const wkup_clkout_sel_out0_parents[] = {
-       "gluelogic_hfosc0_clkout",
+       NULL,
        "gluelogic_lfosc0_clkout",
        "hsdiv4_16fft_main_0_hsdivout2_clk",
        "hsdiv4_16fft_main_1_hsdivout2_clk",
@@ -115,8 +104,13 @@
        "gluelogic_hfosc0_clkout",
 };
 
+static const char * const wkup_clkout_sel_io_out0_parents[] = {
+       "wkup_clkout_sel_out0",
+       "gluelogic_hfosc0_clkout",
+};
+
 static const char * const wkup_clksel_out0_parents[] = {
-       "hsdiv1_16fft_main_15_hsdivout0_clk",
+       "hsdiv2_16fft_main_15_hsdivout0_clk",
        "hsdiv4_16fft_mcu_0_hsdivout0_clk",
 };
 
@@ -143,20 +137,10 @@
        CLK_FIXED_RATE("board_0_mmc1_clk_out", 0, 0),
        CLK_FIXED_RATE("board_0_ospi0_dqs_out", 0, 0),
        CLK_FIXED_RATE("board_0_ospi0_lbclko_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii1_rxc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii1_txc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii2_rxc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rgmii2_txc_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rmii1_ref_clk_out", 0, 0),
-       CLK_FIXED_RATE("board_0_rmii2_ref_clk_out", 0, 0),
        CLK_FIXED_RATE("board_0_tck_out", 0, 0),
-       CLK_FIXED_RATE("cpsw_3guss_main_0_mdio_mdclk_o", 0, 0),
-       CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii1_txc_o", 0, 0),
-       CLK_FIXED_RATE("cpsw_3guss_main_0_rgmii2_txc_o", 0, 0),
        CLK_FIXED_RATE("emmcsd4ss_main_0_emmcsdss_io_clk_o", 0, 0),
        CLK_FIXED_RATE("emmcsd8ss_main_0_emmcsdss_io_clk_o", 0, 0),
        CLK_FIXED_RATE("fss_ul_main_0_ospi_0_ospi_oclk_clk", 0, 0),
-       CLK_DIV("hsdiv0_16fft_mcu_32khz_gen_0_hsdivout0_clk", "gluelogic_hfosc0_clkout", 0x4508030, 0, 7, 0, 0),
        CLK_FIXED_RATE("mshsi2c_main_0_porscl", 0, 0),
        CLK_PLL("pllfracf_ssmod_16fft_main_0_foutvcop_clk", "gluelogic_hfosc0_clkout", 0x680000, 0),
        CLK_DIV("pllfracf_ssmod_16fft_main_0_foutpostdiv_clk_subdiv", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680038, 16, 3, 0, CLK_DIVIDER_ONE_BASED),
@@ -178,6 +162,7 @@
        CLK_DIV("postdiv4_16ff_main_2_hsdivout5_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x682094, 0, 7, 0, 0),
        CLK_DIV("postdiv4_16ff_main_2_hsdivout8_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a0, 0, 7, 0, 0),
        CLK_DIV("postdiv4_16ff_main_2_hsdivout9_clk", "pllfracf_ssmod_16fft_main_2_foutpostdiv_clk", 0x6820a4, 0, 7, 0, 0),
+       CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
        CLK_MUX("main_emmcsd0_io_clklb_sel_out0", main_emmcsd0_io_clklb_sel_out0_parents, 2, 0x108160, 16, 1, 0),
        CLK_MUX("main_emmcsd1_io_clklb_sel_out0", main_emmcsd1_io_clklb_sel_out0_parents, 2, 0x108168, 16, 1, 0),
        CLK_MUX("main_ospi_loopback_clk_sel_out0", main_ospi_loopback_clk_sel_out0_parents, 2, 0x108500, 4, 1, 0),
@@ -185,7 +170,7 @@
        CLK_MUX("main_usb1_refclk_sel_out0", main_usb1_refclk_sel_out0_parents, 2, 0x43008194, 0, 1, 0),
        CLK_DIV("hsdiv0_16fft_main_12_hsdivout0_clk", "pllfracf_ssmod_16fft_main_12_foutvcop_clk", 0x68c080, 0, 7, 0, 0),
        CLK_DIV("hsdiv0_16fft_main_8_hsdivout0_clk", "pllfracf_ssmod_16fft_main_8_foutvcop_clk", 0x688080, 0, 7, 0, 0),
-       CLK_DIV("hsdiv1_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
+       CLK_DIV("hsdiv2_16fft_main_15_hsdivout0_clk", "pllfracf_ssmod_16fft_main_15_foutvcop_clk", 0x68f080, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_0_hsdivout0_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680080, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_0_hsdivout1_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_0_hsdivout2_clk", "pllfracf_ssmod_16fft_main_0_foutvcop_clk", 0x680088, 0, 7, 0, 0),
@@ -195,7 +180,6 @@
        CLK_DIV("hsdiv4_16fft_main_1_hsdivout1_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_1_hsdivout2_clk", "pllfracf_ssmod_16fft_main_1_foutvcop_clk", 0x681088, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
-       CLK_DIV("hsdiv4_16fft_main_2_hsdivout1_clk10", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682084, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_main_2_hsdivout2_clk", "pllfracf_ssmod_16fft_main_2_foutvcop_clk", 0x682088, 0, 7, 0, 0),
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout0_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040080, 0, 7, 0, 0),
        CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_main_0_sysclkout_clk", sam62_pll_ctrl_wrap_main_0_sysclkout_clk_parents, 2, 0x410000, 0),
@@ -203,14 +187,13 @@
        CLK_MUX_PLLCTRL("sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk_parents, 2, 0x4020000, 0),
        CLK_DIV("sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk", "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk", 0x4020118, 0, 5, 0, 0),
        CLK_MUX("clkout0_ctrl_out0", clkout0_ctrl_out0_parents, 2, 0x108010, 0, 1, 0),
-       CLK_MUX("clk_32k_rc_sel_out0", clk_32k_rc_sel_out0_parents, 4, 0x4508058, 0, 2, 0),
-       CLK_MUX("main_cp_gemac_cpts_clk_sel_out0", main_cp_gemac_cpts_clk_sel_out0_parents, 8, 0x108140, 0, 3, 0),
        CLK_MUX("main_emmcsd0_refclk_sel_out0", main_emmcsd0_refclk_sel_out0_parents, 2, 0x108160, 0, 1, 0),
        CLK_MUX("main_emmcsd1_refclk_sel_out0", main_emmcsd1_refclk_sel_out0_parents, 2, 0x108168, 0, 1, 0),
        CLK_MUX("main_gtcclk_sel_out0", main_gtcclk_sel_out0_parents, 8, 0x43008030, 0, 3, 0),
        CLK_MUX("main_ospi_ref_clk_sel_out0", main_ospi_ref_clk_sel_out0_parents, 2, 0x108500, 0, 1, 0),
        CLK_DIV_DEFFREQ("usart_programmable_clock_divider_out0", "hsdiv4_16fft_main_1_hsdivout0_clk", 0x108240, 0, 2, 0, 0, 48000000),
        CLK_MUX("wkup_clkout_sel_out0", wkup_clkout_sel_out0_parents, 8, 0x43008020, 0, 3, 0),
+       CLK_MUX("wkup_clkout_sel_io_out0", wkup_clkout_sel_io_out0_parents, 2, 0x43008020, 24, 1, 0),
        CLK_MUX("wkup_clksel_out0", wkup_clksel_out0_parents, 2, 0x43008010, 0, 1, 0),
        CLK_MUX("main_usart0_fclk_sel_out0", main_usart0_fclk_sel_out0_parents, 2, 0x108280, 0, 1, 0),
        CLK_DIV("hsdiv4_16fft_mcu_0_hsdivout1_clk", "pllfracf_ssmod_16fft_mcu_0_foutvcop_clk", 0x4040084, 0, 7, 0, 0),
@@ -220,29 +203,6 @@
 };
 
 static const struct dev_clk soc_dev_clk_data[] = {
-       DEV_CLK(13, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-       DEV_CLK(13, 3, "main_cp_gemac_cpts_clk_sel_out0"),
-       DEV_CLK(13, 4, "postdiv4_16ff_main_2_hsdivout5_clk"),
-       DEV_CLK(13, 5, "postdiv4_16ff_main_0_hsdivout6_clk"),
-       DEV_CLK(13, 6, "board_0_cp_gemac_cpts0_rft_clk_out"),
-       DEV_CLK(13, 8, "board_0_mcu_ext_refclk0_out"),
-       DEV_CLK(13, 9, "board_0_ext_refclk1_out"),
-       DEV_CLK(13, 10, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
-       DEV_CLK(13, 11, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-       DEV_CLK(13, 13, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 14, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 15, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 16, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 17, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 19, "board_0_rgmii1_rxc_out"),
-       DEV_CLK(13, 20, "board_0_rgmii1_txc_out"),
-       DEV_CLK(13, 22, "board_0_rgmii2_rxc_out"),
-       DEV_CLK(13, 23, "board_0_rgmii2_txc_out"),
-       DEV_CLK(13, 25, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 26, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 27, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(13, 28, "board_0_rmii1_ref_clk_out"),
-       DEV_CLK(13, 29, "board_0_rmii2_ref_clk_out"),
        DEV_CLK(16, 0, "hsdiv4_16fft_main_0_hsdivout1_clk"),
        DEV_CLK(16, 1, "hsdiv4_16fft_main_0_hsdivout2_clk"),
        DEV_CLK(16, 2, "hsdiv4_16fft_main_0_hsdivout3_clk"),
@@ -279,7 +239,7 @@
        DEV_CLK(61, 7, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(61, 8, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(61, 9, "wkup_clksel_out0"),
-       DEV_CLK(61, 10, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+       DEV_CLK(61, 10, "hsdiv2_16fft_main_15_hsdivout0_clk"),
        DEV_CLK(61, 11, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
        DEV_CLK(75, 0, "board_0_ospi0_dqs_out"),
        DEV_CLK(75, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -294,18 +254,16 @@
        DEV_CLK(95, 0, "gluelogic_rcosc_clkout"),
        DEV_CLK(95, 1, "gluelogic_hfosc0_clkout"),
        DEV_CLK(95, 2, "wkup_clksel_out0"),
-       DEV_CLK(95, 3, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+       DEV_CLK(95, 3, "hsdiv2_16fft_main_15_hsdivout0_clk"),
        DEV_CLK(95, 4, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
        DEV_CLK(102, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(102, 1, "board_0_i2c0_scl_out"),
        DEV_CLK(102, 2, "hsdiv4_16fft_main_1_hsdivout0_clk"),
        DEV_CLK(107, 0, "wkup_clksel_out0"),
-       DEV_CLK(107, 1, "hsdiv1_16fft_main_15_hsdivout0_clk"),
+       DEV_CLK(107, 1, "hsdiv2_16fft_main_15_hsdivout0_clk"),
        DEV_CLK(107, 2, "hsdiv4_16fft_mcu_0_hsdivout0_clk"),
-       DEV_CLK(107, 3, "mshsi2c_wkup_0_porscl"),
        DEV_CLK(107, 4, "hsdiv4_16fft_mcu_0_hsdivout1_clk"),
        DEV_CLK(135, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
-       DEV_CLK(136, 0, "hsdiv0_16fft_main_8_hsdivout0_clk"),
        DEV_CLK(140, 0, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(140, 1, "sam62_pll_ctrl_wrap_mcu_0_chip_div1_clk_clk"),
        DEV_CLK(146, 0, "main_usart0_fclk_sel_out0"),
@@ -314,28 +272,20 @@
        DEV_CLK(146, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 20, "clkout0_ctrl_out0"),
        DEV_CLK(157, 21, "hsdiv4_16fft_main_2_hsdivout1_clk"),
-       DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk10"),
+       DEV_CLK(157, 22, "hsdiv4_16fft_main_2_hsdivout1_clk"),
        DEV_CLK(157, 24, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(157, 25, "board_0_ddr0_ck0_out"),
        DEV_CLK(157, 40, "mshsi2c_main_0_porscl"),
        DEV_CLK(157, 77, "sam62_pll_ctrl_wrap_mcu_0_sysclkout_clk"),
-       DEV_CLK(157, 82, "cpsw_3guss_main_0_mdio_mdclk_o"),
        DEV_CLK(157, 83, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
+       DEV_CLK(157, 85, "emmcsd8ss_main_0_emmcsdss_io_clk_o"),
        DEV_CLK(157, 87, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
        DEV_CLK(157, 89, "emmcsd4ss_main_0_emmcsdss_io_clk_o"),
-       DEV_CLK(157, 129, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
-       DEV_CLK(157, 132, "cpsw_3guss_main_0_rgmii1_txc_o"),
-       DEV_CLK(157, 135, "cpsw_3guss_main_0_rgmii2_txc_o"),
-       DEV_CLK(157, 145, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
-       DEV_CLK(157, 158, "wkup_clkout_sel_out0"),
-       DEV_CLK(157, 159, "gluelogic_hfosc0_clkout"),
-       DEV_CLK(157, 160, "gluelogic_lfosc0_clkout"),
-       DEV_CLK(157, 161, "hsdiv4_16fft_main_0_hsdivout2_clk"),
-       DEV_CLK(157, 162, "hsdiv4_16fft_main_1_hsdivout2_clk"),
-       DEV_CLK(157, 163, "postdiv4_16ff_main_2_hsdivout9_clk"),
-       DEV_CLK(157, 164, "clk_32k_rc_sel_out0"),
-       DEV_CLK(157, 165, "gluelogic_rcosc_clkout"),
-       DEV_CLK(157, 166, "gluelogic_hfosc0_clkout"),
+       DEV_CLK(157, 130, "fss_ul_main_0_ospi_0_ospi_oclk_clk"),
+       DEV_CLK(157, 146, "sam62_pll_ctrl_wrap_main_0_sysclkout_clk"),
+       DEV_CLK(157, 159, "wkup_clkout_sel_io_out0"),
+       DEV_CLK(157, 160, "wkup_clkout_sel_out0"),
+       DEV_CLK(157, 161, "gluelogic_hfosc0_clkout"),
        DEV_CLK(161, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(161, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(161, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
@@ -354,14 +304,14 @@
        DEV_CLK(166, 5, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(169, 0, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
        DEV_CLK(169, 1, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
-       DEV_CLK(170, 0, "hsdiv0_16fft_main_12_hsdivout0_clk"),
-       DEV_CLK(170, 1, "board_0_tck_out"),
-       DEV_CLK(170, 2, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
+       DEV_CLK(170, 1, "hsdiv0_16fft_main_12_hsdivout0_clk"),
+       DEV_CLK(170, 2, "board_0_tck_out"),
+       DEV_CLK(170, 3, "sam62_pll_ctrl_wrap_main_0_chip_div1_clk_clk"),
 };
 
-const struct ti_k3_clk_platdata am62x_clk_platdata = {
+const struct ti_k3_clk_platdata am62ax_clk_platdata = {
        .clk_list = clk_list,
-       .clk_list_cnt = 90,
+       .clk_list_cnt = 80,
        .soc_dev_clk_data = soc_dev_clk_data,
-       .soc_dev_clk_data_cnt = 137,
+       .soc_dev_clk_data_cnt = 104,
 };

Jonathan Cormier said:

The generated files are a close match to what is already in the u-boot-2024.04 branch, except for updated Copyright, and "PSC_DEV(36" being removed.

Looks like I didn't say it specifically but the provided files didn't help.

Hi Jonathan,

Apologies for the delayed response again, I was/am out of office this week.

I just noticed the files I shared with you (which were provided to me by our software team) appears to be the same as those from https://git.ti.com/cgit/ti-u-boot/ti-u-boot/tree/arch/arm/mach-k3/r5/am62ax/?h=ti-u-boot-2024.10 (as you mentioned).

Job Sava said:

As a result, the Ethernet device and clocks are not detected in the SPL, which I suspect is due to it not being registered in dev-data.c and clk-data.c.

Can you please provide the exact log showing the error/issue?

-Daolin